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The FPOATM Leader
Field Programmable Object ArrayTM
ArrixTM Family
Product Data Sheet
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10.26.2006
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Notice of Liability Information in this document is provided in relationship with MathStarTM products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document except as provided in MathStar's Terms and Conditions of Sale for such products. MathStar may make any changes to specifications and product descriptions at any time, without notice.
Copyright Notice Copyright (c) 2003 - 2006 by MathStar, Inc. All rights reserved. Any reproduction of these materials without the prior written consent of MathStar, Inc. is strictly prohibited.
Trademarks MathStar, Field Programmable Object Array, FPOA, and Arrix are trademarks of MathStar, Incorporated. All other trademarks, product names, trade names, and service names are the property of their respective owners.
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Published in the United States of America.
Arrix Family Data Sheet
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Table of Contents
Table of Contents
About this Document - - - - - - - - - - - - - - - - - - - - 7 Intended Audience ..................................................................... 7 Related Documents ................................................................... 7 Chapter 1: Introduction - - - - - - - - - - - - - - - - - - - 9 General Description ................................................................... 9 FPOA Architecture ................................................................... 10 Chapter 2: XRAM Hardware - - - - - - - - - - - - - - - - - 13 Overview .................................................................................. 13 External Pins............................................................................ 14 Length and Routing Recommendations . . . . . . . . . . . . . . . . 21 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing Characteristics ............................................................. 26 RLDRAM Details ...................................................................... 31 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Refresh Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 3: GPIO Hardware- - - - - - - - - - - - - - - - - - 35 Overview .................................................................................. 35 External Pins............................................................................ 36 Timing Characteristics ............................................................. 41 Chapter 4: RX Hardware - - - - - - - - - - - - - - - - - - - 43 Overview .................................................................................. 43 External Pins............................................................................ 44 Matched Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Timing Characteristics ............................................................. 48 Chapter 5: TX Hardware - - - - - - - - - - - - - - - - - - - 51 Overview .................................................................................. 51 External Pins............................................................................ 52 Matched Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timing Characteristics ............................................................. 57 Chapter 6: Initialization and Control - - - - - - - - - - - - - 61 Overview .................................................................................. 61 External Pins............................................................................ 62 PROM Load Sequence ............................................................ 65
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Initialization and Reset Sequence............................................ Breakpoint Behavior................................................................. Timing Considerations ............................................................. Supported JTAG and PROM Products .................................... JTAG Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7: Electrical Characteristics - - - - - - - - - - - Overview .................................................................................. Power Supply Requirements.................................................... Absolute Minimum and Maximum Ratings............................... Operating Conditions ............................................................... PLL Power Characteristics....................................................... Power Sequencing ................................................................... Power-up Reset ....................................................................... Decoupling Capacitors ............................................................. Current Fluctuations During Initialization ................................. External Pins ............................................................................ Chapter 8: Clock Characteristics - - - - - - - - - - - - - Core Reference Clock Characteristics ..................................... XRAM Clock Characteristics .................................................... GPIO Clock Characteristics ..................................................... RX Clock Characteristics ......................................................... TX Clock Characteristics.......................................................... PROM Clock Characteristics.................................................... Chapter 9: Thermal Considerations- - - - - - - - - - - - General Considerations ........................................................... Junction Temperature .............................................................. Definition of Terms ................................................................... Forced Convection ................................................................... Natural Convection................................................................... Chapter 10: Packaging Information - - - - - - - - - - - - Overview .................................................................................. Package Dimensions ............................................................... Ball Pattern............................................................................... Recommended PC Board Characteristics ...............................
66 66 67 68 68 68 69 69 69 71 71 74 74 74 75 75 77 79 79 79 80 81 81 82 83 83 83 84 84 85 87 87 87 90 90
Appendix A: External Pins - - - - - - - - - - - - - - - - - 91 Appendix B: Recommended Heat Sinks - - - - - - - - - -121 Appendix C: Periphery Object Naming Convention - - - -125
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Table of Contents
List of Figures
Figure 1-1: FPOA Core and Periphery . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1-2: FPOA Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2-1: Ball Pattern for XRAM (Top-down View) . . . . . . . . . . 14 Figure 2-2: XRAM Clock Routing Option #1 . . . . . . . . . . . . . . . . . 22 Figure 2-3: XRAM Clock Routing Option #2 . . . . . . . . . . . . . . . . . 22 Figure 2-4: XRAM Clock to Data Clock Timing . . . . . . . . . . . . . . . 26 Figure 2-5: XRAM Address and Control Timing . . . . . . . . . . . . . . . 26 Figure 2-6: XRAM MRS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 2-7: XRAM Data Write Timing . . . . . . . . . . . . . . . . . . . . . . 27 Figure 2-8: XRAM Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 2-9: XRAM Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 2-10: XRAM Read Latency. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 2-11: XRAM Write Followed By Read Timing . . . . . . . . . . 29 Figure 2-12: RLDRAM Initialization Sequence . . . . . . . . . . . . . . . . 33 Figure 3-1: Ball Pattern for GPIO (Top-down View). . . . . . . . . . . . 36 Figure 3-2: GPIO Input Timing (Synchronous) . . . . . . . . . . . . . . . . 41 Figure 3-3: GPIO Output Timing (Synchronous) . . . . . . . . . . . . . . . 41 Figure 3-4: GPIO Output Tri-state Timing . . . . . . . . . . . . . . . . . . . . 41 Figure 4-1: Ball Pattern for RX (Top-down View). . . . . . . . . . . . . . 44 Figure 4-2: RX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 4-3: RX DDR 90 Phase-Shifted Timing. . . . . . . . . . . . . . . . 49 Figure 4-4: RX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 4-5: RX SDR 90 Phase-Shifted Timing . . . . . . . . . . . . . . . . 49 Figure 5-1: Ball Pattern for TX (Top-down View). . . . . . . . . . . . . . 52 Figure 5-2: TX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 5-3: TX DDR 90 Phase-Shifted Timing. . . . . . . . . . . . . . . . 57 Figure 5-4: TX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 5-5: TX SDR 90 Phase-Shifted Timing . . . . . . . . . . . . . . . . 58 Figure 6-1: Startup Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 6-2: Ball Pattern for Init & Control (Top-down View) . . . . . 62 Figure 6-3: Start of PROM Load Sequence . . . . . . . . . . . . . . . . . . . 65 Figure 6-4: Completion of PROM Load Sequence. . . . . . . . . . . . . . 65 Figure 6-5: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 6-6: JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 6-7: PROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 7-1: Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 7-2: Current Surge at Startup. . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 10-1: Package Dimensions - Top View . . . . . . . . . . . . . . . . 87 Figure 10-2: Package Dimensions - Side View . . . . . . . . . . . . . . . . 88 Figure 10-3: Package Dimensions - Bottom View. . . . . . . . . . . . . . 88 Figure 11-1: Ball Pattern for FPOA (Top-down View) . . . . . . . . . . 91
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Table of Contents
List of Tables
Table 0-1: Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1-1: Arrix Product Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2-1: XRAM General Characteristics. . . . . . . . . . . . . . . . . . . . 13 Table 2-2: XRAM Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2-3: XRAM Length Recommendations . . . . . . . . . . . . . . . . . 23 Table 2-4: XRAM Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 2-5: XRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . 29 Table 2-6: RLDRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 2-7: RLDRAM Command Codes . . . . . . . . . . . . . . . . . . . . . . 32 Table 3-1: GPIO General Characteristics . . . . . . . . . . . . . . . . . . . . . 35 Table 3-2: GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 3-3: GPIO Timing (using an externally-derived clock) . . . . . 42 Table 3-4: GPIO Timing (using an internally-derived clock). . . . . . 42 Table 4-1: RX General Characteristics . . . . . . . . . . . . . . . . . . . . . . . 43 Table 4-2: RX Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 4-3: RX Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 50 Table 5-1: TX General Characteristics . . . . . . . . . . . . . . . . . . . . . . . 51 Table 5-2: TX Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 5-3: TX Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 59 Table 6-1: Initialization and Control Pins. . . . . . . . . . . . . . . . . . . . . 63 Table 6-2: Breakpoint behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 6-3: JTAG & PROM Timing Characteristics . . . . . . . . . . . . . 68 Table 7-1: Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . 69 Table 7-2: Absolute Minimum and Maximum Ratings . . . . . . . . . . 71 Table 7-3: Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 7-4: Current Surge Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 7-5: Voltage and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 8-1: Core Reference Clock Characteristics. . . . . . . . . . . . . . . 79 Table 8-2: XRAM Clock Characteristics . . . . . . . . . . . . . . . . . . . . . 79 Table 8-3: GPIO Externally-Supplied Clock Characteristics . . . . . . 80 Table 8-4: GPIO Internally-Supplied Clock Characteristics . . . . . . 80 Table 8-5: RX Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 8-6: TX Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 8-7: PROM Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . 82 Table 10-1: Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 11-1: External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 12-1: Forced Convection Heat Sink Options . . . . . . . . . . . . . 121 Table 12-2: Natural Convection Heat Sink Options . . . . . . . . . . . . . 123 Table 13-1: Periphery Object Naming Convention . . . . . . . . . . . . . 125
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About this Document
About this Document
The ArrixTM Family Data Sheet consists of a detailed definition of the hardware development environment. The topics covered include the following: Pin Definitions AC/DC Electrical Characteristics Power and Clock Requirements Thermal Environment Package Information Design Caveats
Intended Audience
This document is intended for hardware designers already familiar with FPOATM concepts. Refer to the Architecture Guide for further information about the FPOA. Detailed descriptions about each object can be found in the Arrix Family Application Developer's Object Reference.
Related Documents
The following documents provide additional information about the FPOA:
Table 0-1 Related Documents Document Arrix Family FPOA Architecture Guide Arrix Family Application Developer's Object Reference Application Developer's Guide Description This document describes the structural and communication architecture of the FPOA. This document provides detailed information about each object in the Arrix family FPOA, including inputs, outputs, configuration parameters, and timing details. This document uses an example application to guide you through creating an FPOA design, connecting and assigning the design, and debugging the design. It includes sample screens, typical circuits, and basic procedures based on the MathStar Design Software.
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Chapter 1 Introduction
Chapter 1 Introduction
General Description
MathStarTM's Field Programmable Object ArrayTM (FPOATM) is a breakthrough field-programmable silicon platform that supports high-speed designs. Unlike FPGAs, which implement functions at the gate level, FPOAs employ higher-order building blocks called "objects." These objects provide a much higher level of abstraction than the gates of conventional FPGAs and perform complex operations at very high clock rates. Each ArrixTM family FPOA contains over 400 objects that are able to pass data and signals to each other through a patented, configurable communication framework. The timing of both the objects and the communication framework is fixed, operating deterministically at frequencies of up to 1 GHz. This deterministic performance eliminates the tedious timing closure design steps associated with previous silicon solutions such as FPGAs and ASICs. MathStar's FPOA allows high-level functions, algorithms, equations, and block diagrams to be quickly, directly, and efficiently realized in high-performance silicon. The Arrix product family is comprised of six products as shown in Table 1-1.
Table 1-1 Arrix Product Family Product MOA2400D-10 MOA2400D-08 MOA2400D-04 MOA2400D-10 R MOA2400D-08 R MOA2400D-04 R Package Information HFCBGA-896 HFCBGA-896 HFCBGA-896 HFCBGA-896, RoHS Complianta HFCBGA-896, RoHS Complianta HFCBGA-896, RoHS Complianta Maximum Operating Frequency 1 GHz 800 MHz 400 MHz 1 GHz 800 MHz 400 MHz
a. RoHS (Restriction on Hazardous Substances) compliance requires limited levels of lead (Pb), mercury, cadmium, hexavalent chromium, polybrominated biphenyl (PBB), and polybrominated diphenyl ethers (PBDE). These levels must be below thresholds proposed by the EU.
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FPOA Architecture
The objects of the FPOA reside in two areas: the core and the periphery. The core objects do most of the computation while the periphery objects provide additional RAM as well as move data between core objects and external devices. Figure 1-1 illustrates these two areas.
Figure 1-1 FPOA Core and Periphery
The core objects are controlled by the FPOA application and are not discussed in this document. However, the electrical characteristics of the following periphery objects are discussed: External RAM (XRAM) -- Each XRAM object provides access to 16 meg by 72-bit (4*16 data bits + 4*2 tag bits) RLDRAM-II. Each Arrix product provides two XRAM objects in the periphery. General Purpose I/O (GPIO) -- The GPIO object provides 48 bidirectional pins of I/O, allowing data transfer between the FPOA and external devices. Each Arrix product provides two GPIO objects in the periphery. Receive (RX) Interface -- The RX interface is used for parallel LVDS input to the FPOA. Each interface has a 17-bit input (16 data bits + 1 tag bit). Each Arrix product provides two RX interfaces in the periphery.
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Chapter 1 Introduction
Transmit (TX) Interface -- The TX interface is used for parallel LVDS output from the FPOA. Each interface has a 17-bit output (16 data bits + 1 tag bit). Each Arrix product provides two TX interfaces in the periphery. Initialization and Control components -- This includes a PROM and JTAG controller, as well as pins for providing an external reference clock. Figure 1-2 illustrates the Arrix family FPOA with all objects labeled.
Figure 1-2 FPOA Objects
For more information on the architecture, see the Arrix Family FPOA Architecture Guide. For more information on the internal characteristics of the FPOA objects, see the Application Developer's Object Reference.
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Chapter 2 XRAM Hardware
Chapter 2 XRAM Hardware
Overview
Each Arrix product provides two external RAM (XRAM) controllers, one on the north side of the periphery and one on the south side. Each XRAM controller provides access to external 36-bit Double-Data-Rate (DDR) Reduced Latency DRAM (RLDRAM-II) memory. The XRAM controller on the north side is associated with the XRAM1_* pins while the controller on the south side is associated with the XRAM2_* pins. Each controller has 21 pins associated with the address bits, 3 pins associated with bank selection, 2 clock pins, 3 control pins, 36 data pins, 8 pins associated with the data output clock, 8 pins associated with the data input strobe, and 21 pins associated with power and termination (20 pins for XRAM2).
Table 2-1 XRAM General Characteristics Characteristic Supported Frequency Description 175 MHz - 266 MHza See Chapter 8: Clock Characteristics for more information. Signal Information 1.8 volts (HSTL) Single-ended 50 impedance (including clock pairs) RLDRAM Configurations One 36-bit RLDRAM for 36 MBytes of memory Two 18-bit RLDRAM for 72 MBytes of memory Four 9-bit RLDRAM for 144 MBytes of memory See "RLDRAM Details" on page 31 for more information. a. The 175 MHz minimum frequency is a Micron requirement for the RLDRAMII device.
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External Pins
Table 2-2 describes the pins associated with the XRAM controller. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Figure 2-1 Ball Pattern for XRAM (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE: XRAM-related balls are shown in black.
Table 2-2 XRAM Pin Descriptions
Pin Number Signal Type Signal Type XRAM 1 A24 B25 A25 F24 E24 E23 A26 D25 B27 XRAM1_ADDR_0 XRAM1_ADDR_1 XRAM1_ADDR_2 XRAM1_ADDR_3 XRAM1_ADDR_4 XRAM1_ADDR_5 XRAM1_ADDR_6 XRAM1_ADDR_7 XRAM1_ADDR_8 O O O O O O O O O HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL XRAM Address bit (LSB) XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit Notes
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Chapter 2 XRAM Hardware
Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number A27 C26 D26 A28 D27 E26 F26 E25 E27 C28 B29 A29 G21 F22 E22 C24 D24 A23 D23 B23 A14 F14 E14 D14 C14 A15 H14 G15 H15 F16 E16 Signal XRAM1_ADDR_9 XRAM1_ADDR_10 XRAM1_ADDR_11 XRAM1_ADDR_12 XRAM1_ADDR_13 XRAM1_ADDR_14 XRAM1_ADDR_15 XRAM1_ADDR_16 XRAM1_ADDR_17 XRAM1_ADDR_18 XRAM1_ADDR_19 XRAM1_ADDR_20 XRAM1_BANK_0 XRAM1_BANK_1 XRAM1_BANK_2 XRAM1_CLK_N XRAM1_CLK_P XRAM1_CNTL_0 XRAM1_CNTL_1 XRAM1_CNTL_2 XRAM1_DATA_0 XRAM1_DATA_1 XRAM1_DATA_2 XRAM1_DATA_3 XRAM1_DATA_4 XRAM1_DATA_5 XRAM1_DATA_6 XRAM1_DATA_7 XRAM1_DATA_8 XRAM1_DATA_9 XRAM1_DATA_10 Type O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL Notes XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit (MSB) XRAM Bank bit XRAM Bank bit XRAM Bank bit XRAM Differential output command clock XRAM Command clock XRAM Control bit (REF#) XRAM Control bit (WE#) XRAM Control bit (CS#) XRAM Data bit (LSB) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit
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Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number A16 B17 A17 G17 E17 D17 H16 C18 A18 A19 F18 E18 D18 A20 B19 G19 A21 A22 F20 E20 B21 E21 D21 D22 C22 E15 Signal XRAM1_DATA_11 XRAM1_DATA_12 XRAM1_DATA_13 XRAM1_DATA_14 XRAM1_DATA_15 XRAM1_DATA_16 XRAM1_DATA_17 XRAM1_DATA_18 XRAM1_DATA_19 XRAM1_DATA_20 XRAM1_DATA_21 XRAM1_DATA_22 XRAM1_DATA_23 XRAM1_DATA_24 XRAM1_DATA_25 XRAM1_DATA_26 XRAM1_DATA_27 XRAM1_DATA_28 XRAM1_DATA_29 XRAM1_DATA_30 XRAM1_DATA_31 XRAM1_DATA_32 XRAM1_DATA_33 XRAM1_DATA_34 XRAM1_DATA_35 XRAM1_DVLD Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Signal Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL Notes XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit (MSB) XRAM Data Valid Input This pin should come from the RLDRAM devices associated with XRAM_DATA[8:0]. XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 9-17) XRAM Differential Output clock (bits 9-17)
B15 C15 C16 D16
XRAM1_DK0_N XRAM1_DK0_P XRAM1_DK1_N XRAM1_DK1_P
O O O O
HSTL HSTL HSTL HSTL
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Chapter 2 XRAM Hardware
Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number D20 C20 D19 E19 D11 C11 F12 E12 B12 A12 D13 C13 A13 C12 C17 C19 C21 C23 C25 C27 C29 D15 E11 E13 E28 G14 G16 G18 G20 G22 Signal XRAM1_DK2_N XRAM1_DK2_P XRAM1_DK3_N XRAM1_DK3_P XRAM1_DQS0_N XRAM1_DQS0_P XRAM1_DQS1_N XRAM1_DQS1_P XRAM1_DQS2_N XRAM1_DQS2_P XRAM1_DQS3_N XRAM1_DQS3_P XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST XRAM1_VDD_PST Type O O O O I I I I I I I I PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Signal Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V Notes XRAM Differential Output clock (bits 18-26) XRAM Differential Output clock (bits 18-26) XRAM Differential Output clock (bits 27-35) XRAM Differential Output clock (bits 27-35) XRAM Differential Input strobe (bits 0-8, DVLD) XRAM Differential Input strobe (bits 0-8, DVLD) XRAM Differential Input strobe (bits 9-17) XRAM Differential Input strobe (bits 9-17) XRAM Differential Input strobe (bits 18-26) XRAM Differential Input strobe (bits 18-26) XRAM Differential Input strobe (bits 27-35) XRAM Differential Input strobe (bits 27-35) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V)
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Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number G23 J15 J16 J18 Signal XRAM1_VDD_PST XRAM1_VREF1 XRAM1_VREF2 XRAM1_VREF3 Type PWR I I I Signal Type 1.8V Analog Analog Analog XRAM 2 AF23 AG24 AH24 AE24 AD23 AF24 AF25 AG25 AJ27 AK27 AC25 AD25 AF26 AH28 AJ29 AK28 AH30 AJ30 AK29 AF27 AG27 AK26 AJ25 AK25 AG26 AH26 XRAM2_ADDR_0 XRAM2_ADDR_1 XRAM2_ADDR_2 XRAM2_ADDR_3 XRAM2_ADDR_4 XRAM2_ADDR_5 XRAM2_ADDR_6 XRAM2_ADDR_7 XRAM2_ADDR_8 XRAM2_ADDR_9 XRAM2_ADDR_10 XRAM2_ADDR_11 XRAM2_ADDR_12 XRAM2_ADDR_13 XRAM2_ADDR_14 XRAM2_ADDR_15 XRAM2_ADDR_16 XRAM2_ADDR_17 XRAM2_ADDR_18 XRAM2_ADDR_19 XRAM2_ADDR_20 XRAM2_BANK_0 XRAM2_BANK_1 XRAM2_BANK_2 XRAM2_CLK_N XRAM2_CLK_P O O O O O O O O O O O O O O O O O O O O O O O O O O HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL XRAM Address bit (LSB) XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit (MSB) XRAM Bank bit XRAM Bank bit XRAM Bank bit XRAM Differential output command clock XRAM Command clock Notes Connect to XRAM I/O Power (1.8V) Connect to XRAM reference voltage (0.9V) Connect to XRAM reference voltage (0.9V) Connect to XRAM reference voltage (0.9V)
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Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number AK24 AJ23 AK23 AF14 AG14 AJ14 AH14 AK15 AK14 AE14 AF15 AJ15 AD15 AJ17 AK19 AK18 AE16 AF16 AG17 AD17 AF17 AH18 AG18 AE18 AF18 AF19 AG19 AJ19 AK20 AJ21 AK21 Signal XRAM2_CNTL_0 XRAM2_CNTL_1 XRAM2_CNTL_2 XRAM2_DATA_0 XRAM2_DATA_1 XRAM2_DATA_2 XRAM2_DATA_3 XRAM2_DATA_4 XRAM2_DATA_5 XRAM2_DATA_6 XRAM2_DATA_7 XRAM2_DATA_8 XRAM2_DATA_9 XRAM2_DATA_10 XRAM2_DATA_11 XRAM2_DATA_12 XRAM2_DATA_13 XRAM2_DATA_14 XRAM2_DATA_15 XRAM2_DATA_16 XRAM2_DATA_17 XRAM2_DATA_18 XRAM2_DATA_19 XRAM2_DATA_20 XRAM2_DATA_21 XRAM2_DATA_22 XRAM2_DATA_23 XRAM2_DATA_24 XRAM2_DATA_25 XRAM2_DATA_26 XRAM2_DATA_27 Type O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL Notes XRAM Control bit (REF#) XRAM Control bit (WE#) XRAM Control bit (CS#) XRAM Data bit (LSB) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit
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Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number AF21 AG21 AG23 AG22 AK22 AH22 AE22 AF22 AG15 Signal XRAM2_DATA_28 XRAM2_DATA_29 XRAM2_DATA_30 XRAM2_DATA_31 XRAM2_DATA_32 XRAM2_DATA_33 XRAM2_DATA_34 XRAM2_DATA_35 XRAM2_DVLD Type I/O I/O I/O I/O I/O I/O I/O I/O I Signal Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL Notes XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit (MSB) XRAM Data Valid Input This pin should come from the RLDRAM devices associated with XRAM_DATA[8:0]. XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 9-17) XRAM Differential Output clock (bits 9-17) XRAM Differential Output clock (bits 18-26) XRAM Differential Output clock (bits 18-26) XRAM Differential Output clock (bits 27-35) XRAM Differential Output clock (bits 27-35) XRAM Differential Input strobe (bits 0-8, DVLD) XRAM Differential Input strobe (bits 0-8, DVLD) XRAM Differential Input strobe (bits 9-17) XRAM Differential Input strobe (bits 9-17) XRAM Differential Input strobe (bits 18-26) XRAM Differential Input strobe (bits 18-26) XRAM Differential Input strobe (bits 27-35) XRAM Differential Input strobe (bits 27-35) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V)
AK16 AK17 AH16 AG16 AF20 AE20 AG20 AH20 AF12 AE12 AH12 AJ12 AG13 AF13 AK13 AJ13 AD12 AD13 AD14
XRAM2_DK0_N XRAM2_DK0_P XRAM2_DK1_N XRAM2_DK1_P XRAM2_DK2_N XRAM2_DK2_P XRAM2_DK3_N XRAM2_DK3_P XRAM2_DQS0_N XRAM2_DQS0_P XRAM2_DQS1_N XRAM2_DQS1_P XRAM2_DQS2_N XRAM2_DQS2_P XRAM2_DQS3_N XRAM2_DQS3_P XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST
O O O O O O O O I I I I I I I I PWR PWR PWR
HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL 1.8V 1.8V 1.8V
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Table 2-2 XRAM Pin Descriptions (Continued)
Pin Number AD16 AD18 AD20 AD21 AD22 AD24 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AH29 AC15 AC18 AD19 Signal XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VREF1 XRAM2_VREF2 XRAM2_VREF3 Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I I I Signal Type 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V Analog Analog Analog Notes Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM reference voltage (0.9V) Connect to XRAM reference voltage (0.9V) Connect to XRAM reference voltage (0.9V)
Length and Routing Recommendations
Given the timing values specified in "Timing Characteristics" on page 26, the guidelines described in this section should be observed.
Clock Alignment
Alignment of clocks at the RLDRAM CK and DK pins must be ensured. To meet the timing of the RLDRAM device, the CK and DK nets must closely match wire lengths and loading. There are two options for connecting the clocks:
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OPTION 1) Use the FPOA CK output to drive the RLDRAM CK input pins and use the FPOA DK output to drive the RLDRAM DK input pins With this option, the XRAM_CK net will naturally be longer and more heavily loaded than the XRAM_DK nets (when multiple RLDRAM devices are used). The XRAM_CK net will see approximately 2-3 pF of load for each RLDRAM device. To meet timing specs, the XRAM_DK traces will need to be lengthened to match the length of the XRAM_CK trace (see Table 2-3) and these traces may need additional capacitors to match the device load of the XRAM_CK net. Place the capacitor near the XRAM_DK termination resistor as shown in Figure 2-2.
Figure 2-2 XRAM Clock Routing Option #1
DK CK
RLDRAM
XRAM_DK
XRAM_DK
DK CK
RLDRAM
FPOA
XRAM_DK
DK
RLDRAM
CK
XRAM_DK
DK
RLDRAM
CK
XRAM_CK
OPTION 2) Use the FPOA DK output to drive both the RLDRAM CK and RLDRAM DK input pins With this option, the timing requirements of CK and DK will naturally be met. The FPOA CK output pin is not used for this option and should be terminated to VTT.
Figure 2-3 XRAM Clock Routing Option #2
DK CK
RLDRAM
XRAM_DK
XRAM_DK
DK
RLDRAM
CK
FPOA
XRAM_DK
DK CK
RLDRAM
XRAM_DK
DK
RLDRAM
CK
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Length Recommendations
Table 2-3 illustrates the minimum and maximum lengths for the XRAM pins. These lengths denote the maximum difference that can be reasonably tolerated to close system timing. Tightening these values will provide more timing margin and more robust RLDRAM operation.
Table 2-3 XRAM Length Recommendationsa Symbol FPOA Pins Minimum Trace Lengthb,c Maximum Trace Lengthb, c Details
CLK
XRAM*_CLK_*
CLK is the trace length used as the basis for the other XRAM trace lengths. CLK - 1" CLK + 2"
ADDR/CNTL /BANK DK DQS DATA
XRAM*_ADDR_* XRAM*_CNTL_* XRAM*_BANK_* XRAM*_DK_* XRAM*_DQS_* XRAM*_DATA_* XRAM*_DVLD_*
CLK - 0.5" CLK - 1" Must be greater than both DK - 1" and DQS - 1"
CLK + 1" CLK + 1" Must be less than both DK and DQS
Lengths for DK traces must match within a one inch tolerance. Lengths for DQS traces must match within a one inch tolerance. Maximum difference between minimum DATA length and maximum ADDR/CNTL/BANK length is four inches.
a. These values assume 266 MHz operation (or less) using a 300 MHz RLDRAM device. b. Values are specified in inches. c. Values assume 175 picoseconds of delay per inch.
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Termination
Each signal is terminated with a 50 resistor to VTT.
Table 2-4 XRAM Termination XRAM 1 XRAM 2 Locate termination resistor near RLDRAM XRAM1_ADDR_0 through XRAM1_ADDR_20 XRAM1_CNTL_2 (CS#) XRAM1_CNTL_0 (REF#) XRAM1_CNTL_1 (WE#) XRAM1_BANK_0 XRAM1_BANK_1 XRAM1_BANK_2 XRAM1_CLK_P and XRAM1_CLK _N (clock pair) XRAM1_DK0_P and XRAM1_DK0_N (clock pair) XRAM1_DK1_P and XRAM1_DK1_N (clock pair) XRAM1_DK2_P and XRAM1_DK2_N (clock pair) XRAM1_DK3_P and XRAM1_DK3_N (clock pair) XRAM2_ADDR_0 through XRAM2_ADDR_20 XRAM2_CNTL_2 (CS#) XRAM2_CNTL_0 (REF#) XRAM2_CNTL_1 (WE#) XRAM2_BANK_0 XRAM2_BANK_1 XRAM2_BANK_2 XRAM2_CLK_P and XRAM2_CLK _N (clock pair) XRAM2_DK0_P and XRAM2_DK0_N (clock pair) XRAM2_DK1_P and XRAM2_DK1_N (clock pair) XRAM2_DK2_P and XRAM2_DK2_N (clock pair) XRAM2_DK3_P and XRAM2_DK3_N (clock pair)
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Table 2-4 XRAM Termination (Continued) XRAM 1 XRAM 2 Locate termination resistor near FPOA XRAM1_DVLD XRAM1_DQS0_P and XRAM1_DQS0_N (clock pair) XRAM1_DQS1_P and XRAM1_DQS1_N (clock pair) XRAM1_DQS2_P and XRAM1_DQS2_N (clock pair) XRAM1_DQS3_P and XRAM1_DQS3_N (clock pair) XRAM2_DVLD XRAM2_DQS0_P and XRAM2_DQS0_N (clock pair) XRAM2_DQS1_P and XRAM2_DQS1_N (clock pair) XRAM2_DQS2_P and XRAM2_DQS2_N (clock pair) XRAM2_DQS3_P and XRAM2_DQS3_N (clock pair)
Locate termination resistor between RLDRAM and FPOA XRAM1_DATA_0 through XRAM1_DATA_35 XRAM2_DATA_0 through XRAM2_DATA_35
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Timing Characteristics
Figure 2-4 illustrates the offset between the XRAM clock and the RLDRAM data clock. Timing values are specified in Table 2-5 on page 29.
Figure 2-4 XRAM Clock to Data Clock Timing
XRAM*_CLK_N XRAM*_CLK_P
tck
tckl
tckh
tckdk
XRAM*_DK*_N XRAM*_DK*_P
tdk
tdkl
tdkh
Figure 2-5 illustrates the minimum and maximum valid times for sending address and control signals.
Figure 2-5 XRAM Address and Control Timing
XRAM*_CLK*_N XRAM*_CLK*_P XRAM*_CNTL_* XRAM*_BANK_* XRAM*_ADDR_*
Valid
tcov(min)
tcov(max)
Figure 2-6 illustrates the minimum cycle time (in number of clock cycles) after issuing the MRS command. This command can be issued automatically by the XRAM controller or manually. For more information, see "Initialization" on page 32.
Figure 2-6 XRAM MRS Timing
XRAM*_CLK_N XRAM*_CLK_P any command
XRAM*_CNTL_*
MRS
NOP
NOP
NOP
tmrsc
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Figure 2-7 illustrates the timing characteristics when writing data to the RLDRAM.
Figure 2-7 XRAM Data Write Timing
XRAM*_DK*_N XRAM*_DK*_P
XRAM*_DATA_*
D0a
D0b
tdw(min)
tdw(max)
Figure 2-8 illustrates the latency when writing data to the RLDRAM and the minimum refresh time before writing to the same bank.
Figure 2-8 XRAM Write Latency
0 XRAM*_CLK*_N XRAM*_CLK*_P XRAM*_CNTL_* XRAM*_ADDR_* XRAM*_BANK_* WRITE A 0 WRITE A 1 WRITE A 0 1 2 3 4 5 6
trc
XRAM*_DK*_N XRAM*_DK*_P XRAM*_DATA_*
twl
D0a
D0b
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Figure 2-9 illustrates the timing characteristics when reading data from the RLDRAM.
Figure 2-9 XRAM Data Read Timing
XRAM*_DQS*_P XRAM*_DQS*_N
tdrvs
XRAM*_DVLD XRAM*_DATA* D0 D1
tdrvh
tdqsdata tdqsdata
Figure 2-10 illustrates the latency when reading data from the RLDRAM and the minimum refresh time before reading from the same bank.
Figure 2-10 XRAM Read Latency
XRAM*_CLK*_N XRAM*_CLK*_P XRAM*_CNTL_* XRAM*_ADDR_* XRAM*_BANK_* READ A 0 READ A 1 READ A 0
trc
XRAM*_DQS*_N XRAM*_DQS*_P XRAM*_DATA_* D0a D0b
trl
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Since writing to the XRAM is one clock slower than reading from the XRAM, there must be a one clock delay for a read command after a write command, as shown in Figure 2-11. This delay is enforced by the controller even if the read command is sent immediately after the write command.
Figure 2-11 XRAM Write Followed By Read Timing
0 XRAM*_CLK*_N XRAM*_CLK*_P XRAM*_CNTL_* WRITE NOP READ 1 2 3 4 5 6 7
twl
XRAM*_DK*_N XRAM*_DK*_P XRAM*_DATA_*
trc
Write DOa
Write D0b
Read D0a
Table 2-5 XRAM Timing Characteristics Parameter Description Clock Timinga tck, tdk tckl, tdkl tckh, tdkh tckdk tfall trise Clock Cycle Time Clock LOW Time Clock HIGH Time Clock to I/O Data Clock Clock Fall Time Clock Rise Time 3.76 ns (266 MHz) 0.47 tck 0.47 tck -300 ps 550 ps 500 ps 5.71 ns (175 MHz) 0.53 tck 0.53 tck 300 ps 850 ps 900 ps Min Max
Address & Control Timing tmrsc tcov Mode Register Set Cycle Time Address & Control Output Valid 6 clock cycles 500 ps 1600 ps
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Table 2-5 XRAM Timing Characteristics (Continued) Parameter Description Data Write Timing tdw trc Data Write Valid Minimum Row Cycle Time 300 ps 900 ps Min Max
Configuration parameter name: min_row_cycle_timeb,c (typically 5 clocks) Configuration parameter name: wr_latencyb,c (typically 6 clocks)
twl
Write Latency
Data Read Timing tdrvs tdrvh tdqsdata trc DVLD to DQS Edge Setup DVLD Hold DQS Edge to Data Edge Minimum Row Cycle Time tck/4 300 ps 0 ps tck/4 + 300 ps tck/4 + 300 ps
Configuration parameter name: min_row_cycle_timeb,c (typically 5 clocks) Configuration parameter name: wr_latency - 1 b,c (typically 5 clocks)
trl
Read Latency
a. See Chapter 8: Clock Characteristics for additional clock information. b. See the Application Developer's Object Reference for information about configuring this parameter. c. See the RLDRAM Data Sheet for constraints for each RLDRAM configuration.
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RLDRAM Details
The following section describes some key characteristics of the RLDRAMII hardware. Visit http://www.micron.com/rldram for more information.
Configurations
The XRAM controller has been designed to directly connect to the 288 Mbit RLDRAM specification and can support one, two, or four parallel memory device configurations at the board level. Table 2-6 details these configurations.
Table 2-6 RLDRAM Configurations Number of Devices 1 2 4 Component Type 8M x 36 16M x 18 32M x 9 Total Memory Size Per Interface 36 MBytes 72 MBytes 144 MBytes Model
Micron MT49H8M36FM Micron MT49H16M18FM Micron MT49H32M9FM
Bank Selection
Once one of the eight internal banks within an RLDRAM is accessed, it cannot be accessed again for the minimum row cycle time (trc) as shown in Figure 2-8 on page 27 and Figure 2-10 on page 28. Maximum bandwidth is achieved by accessing another bank that has met its minimum row cycle time requirement. The XRAM controller automatically guarantees that minimum row cycle time is met for all memory accesses by inserting wait states as needed. For more information on optimizing RLDRAM access timing, see the Application Developer's Object Reference.
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Command Codes
The following table lists the command codes available via the three control pins (XRAM*_CNTL_*). See the Application Developer's Object Reference for more information on issuing XRAM commands.
Table 2-7 RLDRAM Command Codes Command NOP CNTL_2 (CS#) H CNTL_1 (WE#) X CNTL_0 (REF#) X Description Device deselect / No operation. This command is used to perform no operation, which essentially deselects the chip. Operations already in progress are not affected. Mode register set. This command stores the data for controlling the operating modes of the memory. It programs the burst length, test mode, and I/O options. This command can automatically be issued by the XRAM controller. Read. This command is used to initiate a burst read access to a bank. Write. This command is used to initiate a burst write access to a bank. Auto refresh. This command is used during normal operation to refresh the memory content of a bank. The command is nonpersistent and must be issued each time a refresh is required.
MRS
L
L
L
READ WRITE AREF
L L L
H L H
H H L
NOTES: 1. H = Logic high 2. L = Logic low 3. X = "Don't care"
Initialization
The RLDRAM can be initialized automatically by the controller at startup. This option is configurable via the configuration parameter "init_rldram21." The application can also initiate initialization through an XRAM controller command code. In either case, the XRAM controller performs the following initialization sequence: 1. Power is applied and the clock starts as soon as the XRAM is configured. 2. The controller waits for a time specified by the configuration parameter "init_wait_tc." This time must be at least 200 s.
1. See the Application Developer's Object Reference for information on this and other application-controlled configuration parameters.
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3. Three consecutive MRS commands are issued: two dummies plus one valid MRS1. 4. After the mode register set cycle time (tmrsc from Table 2-5 on page 29), eight AREF commands are issued, one on each bank separated by 2052 cycles. 5. After the row cycle time (trc from Table 2-5 on page 29), the chip is ready for normal operation.
Figure 2-12 RLDRAM Initialization Sequence
XRAM*_CLK*_N XRAM*_CLK*_P XRAM*_CNTL_*
NOP NOP MRS MRS MRS AREF
Bank 1
AREF
Bank 8
any command
init_wait_tc
(200 s min.)
tmrsc
7 x 2052 cycles
trc
(each AREF is separated by 2052 XRAM clock cycles)
For manual initialization, consult the RLDRAM Data Sheet for timing considerations.
Refresh Behavior
There are several ways to configure the XRAM controller's refresh behavior: Auto refresh -- Refresh can be performed automatically by the controller or it can be performed manually by the application. By default, automatic refresh is turned on. Refresh style -- Refresh can occur as a burst of eight refresh commands (one for each bank), or it can occur one bank at a time. By default, refresh will occur as a burst. Additionally, burst refresh can occur one or more consecutive times. This capability is useful for applications such as video processing applications where the refresh occurs during the video synchronization period. Refresh interval count -- Regardless or which refresh style is selected, the number of XRAM clocks between refreshes is configurable. These values are all controlled through configuration parameters, which are described in more detail in the Application Developer's Object Reference.
1. Although the MRS value is configurable by the application developer ("rldram2_mrs"), the XRAM controller requires a burst length of two (bits[4:3] = 00) and that the RLDRAM is in non-multiplexed mode (bit[5] = 0).
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Chapter 3 GPIO Hardware
Chapter 3 GPIO Hardware
Overview
The GPIO interface object facilitates communication between the FPOA and external devices. Each Arrix product provides two GPIO interfaces, one on the north side of the periphery and one on the south side. Each interface provides 48 bidirectional pins operating at LVCMOS signaling levels. The GPIO interface on the north side is associated with the GPIO1_* pins while the interface on the south side is associated with the GPIO2_* pins. Each interface has 48 data pins, 1 clock pin, and 12 pins associated with power. The direction of the data pins (i.e. input / output) can be configured statically at initialization or dynamically at runtime. Data can be received/transmitted synchronously or asynchronously. See the Application Developer's Object Reference for more information on GPIO interface configurations.
Table 3-1 GPIO General Characteristics Characteristic Supported Frequency Description 0 MHz - 100 MHz See Chapter 8: Clock Characteristics for more information. Signal Control On a per nibble basis, GPIO signals may be configured for: Synchronous or asynchronous clocking Input, output, or bidirection operation Signal Information 2.5 volts (LVCMOS) Inputs are 3.3 volt tolerant 16mA drive for the GPIO clocks Single-ended 50 impedance No termination Load Per Signal 10pF @ 100MHz 20pF @ 66MHz
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External Pins
Table 3-2 describes the pins associated with the GPIO interface. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Figure 3-1 Ball Pattern for GPIO (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE: GPIO-related balls are shown in black.
Table 3-2 GPIO Pin Descriptions
Pin Number Signal Type Signal Type GPIO 1 D1 E1 E3 G5 F4 C2 C1 E4 F6 E5 GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_5 GPIO1_6 GPIO1_7 GPIO1_8 GPIO1_9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit Notes
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Table 3-2 GPIO Pin Descriptions (Continued)
Pin Number H7 G7 D4 D3 B1 A2 C4 B3 A3 D5 D6 C6 B5 A4 E7 F8 E6 C8 A6 A5 B7 D8 E8 G9 E9 A8 A7 B9 A9 D9 F10 Signal GPIO1_10 GPIO1_11 GPIO1_12 GPIO1_13 GPIO1_14 GPIO1_15 GPIO1_16 GPIO1_17 GPIO1_18 GPIO1_19 GPIO1_20 GPIO1_21 GPIO1_22 GPIO1_23 GPIO1_24 GPIO1_25 GPIO1_26 GPIO1_27 GPIO1_28 GPIO1_29 GPIO1_30 GPIO1_31 GPIO1_32 GPIO1_33 GPIO1_34 GPIO1_35 GPIO1_36 GPIO1_37 GPIO1_38 GPIO1_39 GPIO1_40 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Notes GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit
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Table 3-2 GPIO Pin Descriptions (Continued)
Pin Number C10 A10 H10 E10 D10 A11 B11 D7 C3 C5 C7 C9 E2 G6 G8 G10 G12 H8 H9 H12 Signal GPIO1_41 GPIO1_42 GPIO1_43 GPIO1_44 GPIO1_45 GPIO1_46 GPIO1_47 GPIO1_CLK GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_VDD_PST Type I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Signal Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V GPIO 2 AG1 AH1 AJ1 AG3 AH2 AJ2 AK2 AJ3 AG2 AG4 GPIO2_0 GPIO2_1 GPIO2_2 GPIO2_3 GPIO2_4 GPIO2_5 GPIO2_6 GPIO2_7 GPIO2_8 GPIO2_9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit Notes GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO clocka Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V)
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Chapter 3 GPIO Hardware
Table 3-2 GPIO Pin Descriptions (Continued)
Pin Number AH4 AF5 AG5 AK3 AC7 AD7 AF6 AG6 AB9 AC9 AB8 AC8 AE8 AF8 AK4 AH6 AJ5 AK5 AD9 AG8 AK6 AH8 AJ7 AK7 AK8 AE10 AF10 AF9 AG9 AG10 AH10 Signal GPIO2_10 GPIO2_11 GPIO2_12 GPIO2_13 GPIO2_14 GPIO2_15 GPIO2_16 GPIO2_17 GPIO2_18 GPIO2_19 GPIO2_20 GPIO2_21 GPIO2_22 GPIO2_23 GPIO2_24 GPIO2_25 GPIO2_26 GPIO2_27 GPIO2_28 GPIO2_29 GPIO2_30 GPIO2_31 GPIO2_32 GPIO2_33 GPIO2_34 GPIO2_35 GPIO2_36 GPIO2_37 GPIO2_38 GPIO2_39 GPIO2_40 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Notes GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit
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Table 3-2 GPIO Pin Descriptions (Continued)
Pin Number AK9 AJ9 AK10 AK11 AF11 AG11 AJ11 AG7 Y9 AB10 AC10 AD6 AD8 AD10 AE6 AF4 AF7 AH3 AH5 AH7 AH9 AH11 Signal GPIO2_41 GPIO2_42 GPIO2_43 GPIO2_44 GPIO2_45 GPIO2_46 GPIO2_47 GPIO2_CLK GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST GPIO2_VDD_PST Type I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Signal Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Notes GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO clocka Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) Connect to GPIO power (2.5V)
a. 16mA drive for the GPIO clock
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Timing Characteristics
Figure 3-2 illustrates the timing characteristics when the GPIO interface is used for input.
Figure 3-2 GPIO Input Timing (Synchronous)
tper
GPIO Clock
GPIO Data
D0
tdis tdih
Figure 3-3 illustrates the timing characteristics when the GPIO interface is used for output.
Figure 3-3 GPIO Output Timing (Synchronous)
GPIO Clock
GPIO Data
D0
D1
tdov
Figure 3-4 illustrates the timing characteristics when the data pins enter and leave tri-state.
Figure 3-4 GPIO Output Tri-state Timing
GPIO Clock
GPIO Data
tdoz1
tdoz2
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For information about the latency to/from the party line signals consult the Application Developer's Object Reference.
Table 3-3 GPIO Timing (using an externally-derived clock) Parameter Description Clock Timinga tper GPIO Clock Period Input Timing tdis tdih Data Input Setup Data Input Hold Output Timing tdov tdoz1 tdoz2 Data Output Valid Data Output Enter Tristate Data Output Exit Tristate 2.0 ns 1.0 ns 2.0 ns 5.0 ns 2.5 ns 5.0 ns 0.500 ns 0.500 ns 10 ns Min Max
a. See Chapter 8: Clock Characteristics for additional clock information.
Table 3-4 GPIO Timing (using an internally-derived clock) Parameter Description Clock Timinga tper GPIO Clock Period Input Timing tdis tdih Data Input Setup Data Input Hold Output Timing tdov tdoz1 tdoz2 Data Output Valid Data Output Enter Tristate Data Output Exit Tristate 1.0 ns 0.3 ns 1.0 ns 3.0 ns 1.0 ns 3.0 ns 2.0 ns 0 ns 10 ns Min Max
a. See Chapter 8: Clock Characteristics for additional clock information.
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Chapter 4 RX Hardware
Chapter 4 RX Hardware
Overview
The RX interface is used for high-speed parallel LVDS input to the FPOA. Each Arrix product provides two RX interfaces, one on the east side of the periphery and one on the west side. The RX interface on the east side is associated with the RX1_* pins while the interface on the west side is associated with the RX2_* pins. Each signal has both a negative (RX*_N) and a positive (RX*_P) pin comprising the differential pair. Each interface has 1 clock pin pair, 1 control pin pair, 16 data pin pairs, and 10 pins associated with power.
Table 4-1 RX General Characteristics Characteristic Data Rate Supported Frequency Signal Information Description SDR / DDR (programmable) 116 MHz - 500 MHz (DDR) 116 MHz - 640 MHz (SDR) 1.25 V (LVDS) Differential pairs, 100 impedance
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External Pins
Table 4-2 describes the pins associated with the RX interface. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Figure 4-1 Ball Pattern for RX (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE: RX-related balls are shown in black.
Table 4-2 RX Pin Descriptions
Pin Number Signal Type Signal Type Notes
Receive Datapath 1 V5 V4 AA5 AA6 T2 T1 U2 U3 U5 RX1_CLK1_N RX1_CLK1_P RX1_CNTL_N RX1_CNTL_P RX1_DATA_0_N RX1_DATA_0_P RX1_DATA_1_N RX1_DATA_1_P RX1_DATA_2_N I I I I I I I I I LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Receive Clock Receive Clock Receive Control bit Receive Control bit Receive Data bit (LSB) Receive Data bit Receive Data bit Receive Data bit Receive Data bit
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Table 4-2 RX Pin Descriptions (Continued)
Pin Number U6 V2 V1 W2 W3 W6 W5 Y1 Y2 Y4 Y5 AA2 AA3 AB1 AB2 AC3 AC2 AB4 AB5 AD1 AD2 AD4 AD5 AE2 AE3 AF1 AF2 U1 U4 W1 W4 Signal RX1_DATA_2_P RX1_DATA_3_N RX1_DATA_3_P RX1_DATA_4_N RX1_DATA_4_P RX1_DATA_5_N RX1_DATA_5_P RX1_DATA_6_N RX1_DATA_6_P RX1_DATA_7_N RX1_DATA_7_P RX1_DATA_8_N RX1_DATA_8_P RX1_DATA_9_N RX1_DATA_9_P RX1_DATA_10_N RX1_DATA_10_P RX1_DATA_11_N RX1_DATA_11_P RX1_DATA_12_N RX1_DATA_12_P RX1_DATA_13_N RX1_DATA_13_P RX1_DATA_14_N RX1_DATA_14_P RX1_DATA_15_N RX1_DATA_15_P RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST Type I I I I I I I I I I I I I I I I I I I I I I I I I I I PWR PWR PWR PWR Signal Type LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS 2.5V 2.5V 2.5V 2.5V Notes Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit (MSB) Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V
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Table 4-2 RX Pin Descriptions (Continued)
Pin Number AA1 AA4 AC1 AC4 AE1 AE4 Signal RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST RX1_VDD_PST Type PWR PWR PWR PWR PWR PWR Signal Type 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Notes Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V
Receive Datapath 2 P26 P25 M26 M25 T28 T29 T26 T25 R29 R30 R27 R26 P28 P29 N29 N30 N27 N26 M28 M29 L30 L29 L27 L26 RX2_CLK1_N RX2_CLK1_P RX2_CNTL_N RX2_CNTL_P RX2_DATA_0_N RX2_DATA_0_P RX2_DATA_1_N RX2_DATA_1_P RX2_DATA_2_N RX2_DATA_2_P RX2_DATA_3_N RX2_DATA_3_P RX2_DATA_4_N RX2_DATA_4_P RX2_DATA_5_N RX2_DATA_5_P RX2_DATA_6_N RX2_DATA_6_P RX2_DATA_7_N RX2_DATA_7_P RX2_DATA_8_N RX2_DATA_8_P RX2_DATA_9_N RX2_DATA_9_P I I I I I I I I I I I I I I I I I I I I I I I I LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Receive Clock Receive Clock Receive Control bit Receive Control bit Receive Data bit (LSB) Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit
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Table 4-2 RX Pin Descriptions (Continued)
Pin Number J30 J29 K28 K29 K25 K26 H29 H28 J27 J26 G29 G30 H30 K24 K27 K30 M24 M27 M30 P24 P27 P30 R24 T27 T30 Signal RX2_DATA_10_N RX2_DATA_10_P RX2_DATA_11_N RX2_DATA_11_P RX2_DATA_12_N RX2_DATA_12_P RX2_DATA_13_N RX2_DATA_13_P RX2_DATA_14_N RX2_DATA_14_P RX2_DATA_15_N RX2_DATA_15_P RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST RX2_VDD_PST Type I I I I I I I I I I I I PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Signal Type LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Notes Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit Receive Data bit (MSB) Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V
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Matched Lengths
Match length tolerance is 2/3 inch maximum for each group.
Group 1 RX1_DATA_x RX1_CLK1_x RX1_CNTL_x Group 2 RX2_DATA_x RX2_CLK1_x RX2_CNTL_x
Termination
Internal termination is 100 across the differential pairs. No external termination is required.
Timing Characteristics
Figure 4-2 illustrates the timing characteristics in DDR mode when the clock is aligned with the data (i.e. in-phase). Note that these same timing parameters apply when using an inverted clock (though the clock is 180 offset).
Figure 4-2 RX DDR In-Phase Timing
tper RX Clock
RX Data & Control tdv
D0 tdv tdv
D1
tdv
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Figure 4-3 illustrates the timing characteristics in DDR mode when the clock is 90 phase-shifted with the data.
Figure 4-3 RX DDR 90 Phase-Shifted Timing
RX Clock
RX Data & Control
D0 tds tdh
D1 tds tdh
Figure 4-4 illustrates the timing characteristics in SDR mode when the clock is aligned with the data.
Figure 4-4 RX SDR In-Phase Timing
RX Clock
RX Data & Control tdv
D0
tdv
Figure 4-5 illustrates the timing characteristics in SDR mode when the clock is 90 phase-shifted with the data.
Figure 4-5 RX SDR 90 Phase-Shifted Timing
RX Clock
RX Data & Control tds
D0
D1
tdh
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Table 4-3 RX Timing Characteristics Parameter Description Min Input Timing tdv tds tdh SDR/DDR Data Valid SDR/DDR 90 Phase-Shifted Data Setup SDR/DDR 90 Phase-Shifted Data Hold Clock Timinga tper Clock Period 1.56 ns (640 MHz SDR) 2.0 ns (500 MHz DDR) RX DLL Lock Time 1200 clocks 8.62 ns (116 MHz) tper/4 175 ps tper/4 + 175 ps 175 ps 175 ps Max
a. See Chapter 8: Clock Characteristics for additional clock information.
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Chapter 5 TX Hardware
Chapter 5 TX Hardware
Overview
The TX interface is used for high-speed parallel LVDS output from the FPOA. Each Arrix product provides two TX interfaces, one on the east side of the periphery and one on the west side. The TX interface on the east side is associated with the TX1_* pins while the interface on the west side is associated with the TX2_* pins. Each signal has both a negative (TX*_N) and a positive (TX*_P) pin comprising the differential pair. Each interface has 1 reference clock pin, 1 transmit clock pin pair, 1 control pin pair, 16 data pin pairs, and 17 pins associated with power and ground.
Table 5-1 TX General Characteristics Characteristic Data Rate Supported Frequency Description SDR / DDR (programmable) 18.75 MHz - 500 MHz (DDR) 18.75 MHz - 640 MHz (SDR) See Chapter 8: Clock Characteristics for more information. Signal Information 1.25 V (LVDS) Differential pairs, 100 impedance
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External Pins
Table 5-2 describes the pins associated with the TX interface. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Figure 5-1 Ball Pattern for TX (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE: TX-related balls are shown in black.
Table 5-2 TX Pins
Pin Number Signal Type Signal Type Notes
Transmit Datapath 1 K9 TPLL1_AVDD PWR Analog Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information. Do not connect 18.75 - 37.5Mhz reference clock input for Transmit PLL Transmit Clock Transmit Clock
J10
TPLL1_AVSS
GND
Analog
J8 J9 N2 N3
TPLL1_CAP TPLL1_REF TX1_CLK1_N TX1_CLK1_P
I I O O
Analog LVCMOS LVDS LVDS
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Table 5-2 TX Pins (Continued)
Pin Number L5 L6 R3 R2 R5 R6 P1 P2 P4 P5 N5 N6 M1 M2 M4 M5 L2 L3 K2 K1 K4 K5 J3 J2 J5 J6 H1 H2 H4 H5 G2 Signal TX1_CNTL_N TX1_CNTL_P TX1_DATA_0_N TX1_DATA_0_P TX1_DATA_1_N TX1_DATA_1_P TX1_DATA_2_N TX1_DATA_2_P TX1_DATA_3_N TX1_DATA_3_P TX1_DATA_4_N TX1_DATA_4_P TX1_DATA_5_N TX1_DATA_5_P TX1_DATA_6_N TX1_DATA_6_P TX1_DATA_7_N TX1_DATA_7_P TX1_DATA_8_N TX1_DATA_8_P TX1_DATA_9_N TX1_DATA_9_P TX1_DATA_10_N TX1_DATA_10_P TX1_DATA_11_N TX1_DATA_11_P TX1_DATA_12_N TX1_DATA_12_P TX1_DATA_13_N TX1_DATA_13_P TX1_DATA_14_N Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Signal Type LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Notes Transmit Control bit Transmit Control bit Transmit Data bit (LSB) Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit
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Table 5-2 TX Pins (Continued)
Pin Number G3 F1 F2 G1 G4 J1 J4 J7 L1 L4 L7 N1 N4 N7 R1 R4 R7 R8 U09 Signal TX1_DATA_14_P TX1_DATA_15_N TX1_DATA_15_P TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VDD_PST TX1_VREF Type O O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I Signal Type LVDS LVDS LVDS 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 1.2V Analog Transmit Datapath 2 Y23 TPLL2_AVDD PWR Analog Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information. Do not connect 18.75 - 37.5MHz reference clock input for Transmit PLL Transmit Clock Transmit Clock Transmit Control bit Notes Transmit Data bit Transmit Data bit Transmit Data bit (MSB) LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS TX1 Analog 1.2V common mode voltage reference
Y22
TPLL2_AVSS
GND
Analog
AA23 AC21 W27 W26 AB29
TPLL2_CAP TPLL2_REF TX2_CLK1_N TX2_CLK1_P TX2_CNTL_N
I I O O O
Analog LVCMOS LVDS LVDS LVDS
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Table 5-2 TX Pins (Continued)
Pin Number AB28 U27 U26 V28 V29 V26 V25 W30 W29 Y29 Y28 Y26 Y25 AA30 AA29 AA26 AA27 AB25 AB26 AC29 AC30 AC27 AC26 AD28 AD29 AE27 AE26 AE30 AE29 AF29 AF28 Signal TX2_CNTL_P TX2_DATA_0_N TX2_DATA_0_P TX2_DATA_1_N TX2_DATA_1_P TX2_DATA_2_N TX2_DATA_2_P TX2_DATA_3_N TX2_DATA_3_P TX2_DATA_4_N TX2_DATA_4_P TX2_DATA_5_N TX2_DATA_5_P TX2_DATA_6_N TX2_DATA_6_P TX2_DATA_7_N TX2_DATA_7_P TX2_DATA_8_N TX2_DATA_8_P TX2_DATA_9_N TX2_DATA_9_P TX2_DATA_10_N TX2_DATA_10_P TX2_DATA_11_N TX2_DATA_11_P TX2_DATA_12_N TX2_DATA_12_P TX2_DATA_13_N TX2_DATA_13_P TX2_DATA_14_N TX2_DATA_14_P Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Signal Type LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Notes Transmit Control bit Transmit Data bit (LSB) Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit Transmit Data bit
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Table 5-2 TX Pins (Continued)
Pin Number AG30 AG29 V24 V27 V30 W24 Y24 Y27 Y30 AB27 AB30 AD26 AD27 AD30 AF30 U23 Signal TX2_DATA_15_N TX2_DATA_15_P TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VDD_PST TX2_VREF Type O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I Signal Type LVDS LVDS 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 1.2V Analog Notes Transmit Data bit Transmit Data bit (MSB) LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS 2.5V LVDS TX2 Analog 1.2V common mode voltage reference
Matched Lengths
Match length tolerance is 2/3 inch maximum for each group.
Group 1 TX1_DATA_x TX1_CLK1_x TX1_CNTL_x Group 2 TX2_DATA_x TX2_CLK1_x TX2_CNTL_x
Termination
External termination is 100 across the differential pairs at load.
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Chapter 5 TX Hardware
Timing Characteristics
Figure 5-2 illustrates the timing characteristics in DDR mode when the clock is aligned with the data (i.e. in-phase). Note that these same timing parameters apply when using an inverted clock (though the clock is 180 offset).
Figure 5-2 TX DDR In-Phase Timing
tper TX Clock
TX Data & Control tdv
D0 tdv tdv
D1
tdv
Figure 5-3 illustrates the timing characteristics in DDR mode when the clock is 90 phase-shifted with the data.
Figure 5-3 TX DDR 90 Phase-Shifted Timing
TX Clock
TX Data &Control
D0 tds tdh
D1 tds tdh
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Figure 5-4 illustrates the timing characteristics in SDR mode when the clock is aligned with the data.
Figure 5-4 TX SDR In-Phase Timing
TX Clock
TX Data & Control tdv
D0
tdv
Figure 5-5 illustrates the timing characteristics in SDR mode when the clock is 90 phase-shifted with the data.
Figure 5-5 TX SDR 90 Phase-Shifted Timing
TX Clock
TX Data & Control tds
D0
D1
tdh
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Table 5-3 TX Timing Characteristics Parameter Description Min Input Timing tdv tds tdh SDR/DDR Data Valid SDR/DDR 90 Phase-Shifted Data Setup SDR/DDR 90 Phase-Shifted Data Hold Clock Timinga tper Clock Period 1.56 ns (640 MHz SDR) 2.0 ns (500 MHz DDR) PLL Lock Time 15 s 53.33 ns (18.75 MHz) -175 ps tper/4.5 175 ps tper/4.5 175 ps 175 ps Max
a. See Chapter 8: Clock Characteristics for additional clock information.
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Chapter 6 Initialization and Control
Chapter 6 Initialization and Control
Overview
Figure 6-1 illustrates the startup flow for the FPOA.
Figure 6-1 Startup Flow
Check for PROM, JTAG
Power-on
Load & Start Periphery Objects
Load Core Objects
Load IRAM Memory
Enable Clocks
Initialization
Normal Operation
Control / Debug
At power-on, the PROM_DISABLE signal indicates whether a PROM is present. If deasserted, the PROM controller automatically accesses the PROM to acquire load information. If no PROM is present, the controller waits for configuration information via the JTAG controller. The high-speed clock used in the FPOA is disabled while clocks operating at slower frequencies shift in configuration information via scan chains. (See "PROM Load Sequence" on page 65 for more information.) The periphery objects are loaded first, followed by the core objects. Note that the periphery objects start before normal operation. After all objects are loaded (and the periphery objects are started), the clocks are enabled, chip registers initialize to their configured values, and the application begins running.
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Significant current surges occur when the FPOA transitions from configuration load to initialization, and from initialization to normal operation. See "Current Fluctuations During Initialization" on page 75 for further detail. During normal operation, the JTAG controller can assume control of the FPOA at any time. It can halt operation and observe the state of any of the objects within the FPOA. It can also reset the chip.
External Pins
Table 6-1 describes the pins associated with the PROM interface, the JTAG interface, the Core PLL, as well as other miscellaneous control pins. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Figure 6-2 Ball Pattern for Init & Control (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE: Initialization and Control balls are shown in black.
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Table 6-1 Initialization and Control Pins
Pin Number Signal Type Signal Type PROM Interface G25 G27 F29 PROM_CEN PROM_CLK PROM_CLKDIV O I I LVCMOS LVCMOS LVCMOS PROM Chip Enable (low active) PROM Clock Input PROM Clock Divider Input 0 = Divide by 2 1 = Divide by 4 PROM Clock Output (PROM_CLK divided by 2 or 4, as specified by PROM_CLKDIV above) PROM Data bit (LSB) PROM Data bit PROM Data bit PROM Data bit PROM Data bit PROM Data bit PROM Data bit PROM Data bit (MSB) PROM Disable Input PROM Output Enable PROM Serial/Parallel mode select 0 = 8-bit connection 1 = 1-bit connection Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Connect to 2.5V Notes
F27
PROM_CLKO
O
LVCMOS
E30 C30 D29 E29 F28 G26 H26 H27 H24 H25 J24
PROM_DATA_0 PROM_DATA_1 PROM_DATA_2 PROM_DATA_3 PROM_DATA_4 PROM_DATA_5 PROM_DATA_6 PROM_DATA_7 PROM_DISABLE PROM_OE PROM_SERIAL
I I I I I I I I I O I
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
B30 D30 F25 F30 G24
PROM_VDD_PST PROM_VDD_PST PROM_VDD_PST PROM_VDD_PST PROM_VDD_PST
PWR PWR PWR PWR PWR
2.5V 2.5V 2.5V 2.5V 2.5V Core PLL
AA8
CPLL_AVDD
PWR
Analog
Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information.
Y8
CPLL_AVSS
GND
Analog
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Table 6-1 Initialization and Control Pins (Continued)
Pin Number Y6 AA9 Signal CPLL_CAP CPLL_REF Type I I Signal Type Analog LVCMOS Test & Reset AA7 Y7 AA21 AB21 AC22 AB24 AC23 AB23 AC24 AB22 AA24 T4 T5 U29 U30 CLOCK_N CLOCK_P JTAG_VDD_PST JTAG_VDD_PST RESETn TCLK TDI TDO TESTMODE TMS TRSTn TX1_TEST_N TX1_TEST_P TX2_TEST_N TX2_TEST_P I I PWR PWR I I I O I I I O O O O LVDS LVDS 2.5V 2.5V LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVDS LVDS LVDS LVDS Core clock bypass input Core clock bypass input Connect to 2.5V Connect to 2.5V FPOA Reset (low active) JTAG Test Clock Input This input has a built-in pullup resistor. JTAG Test Data Input This input has a built-in pullup resistor. JTAG Test Data Output Connect to ground This input has a built-in pulldown resistor. JTAG Test Mode Select This input has a built-in pullup resistor. JTAG Test Reset (low active) This input has a built-in pullup resistor. Production test pin - do not connect Production test pin - do not connect Production test pin - do not connect Production test pin - do not connect Notes Do not connect 18.75 - 37.5 MHz reference clock input for Core PLL
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PROM Load Sequence
Figure 6-3 illustrates the sequence of events that occurs during PROM load.
Figure 6-3 Start of PROM Load Sequence
PROM_CLK RESETn PROM_CEN PROM_OE PROM_CLKO PROM_DATA_*
Byte 0
1
2
...
The reset signal (RESETn) initiates the loading process. Reset forces the output enable signal (PROM_OE) low in order to initialize the PROM. The chip enable signal (PROM_CEN) goes active low and the output enable signal goes active high to enable the PROM device to be read. The PROM clock begins, causing the PROM to shift read data into the FPOA. When the PROM controller detects that the load sequence is completed, the signals PROM_CEN and PROM_OE deactivate. Figure 6-4 illustrates this sequence. The controller then takes the FPOA through its final initialization stage and onto normal operation.
Figure 6-4 Completion of PROM Load Sequence
PROM_CLK PROM_CEN PROM_OE PROM_CLKO PROM_DATA_*
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Initialization and Reset Sequence
Figure 6-5 illustrates the startup sequence after reset is signaled (RESETn, pin #AC22).
Figure 6-5 Reset Timing
HW Reset Periphery I/O Periphery Clocks I/O Config Done Config Done
Valid high, low, or tri-state, based on configuration Actively changing based on core object control
HW reset to tri-state (20 ns)
periphery load
core object load & IRAM memory load
initialization
normal operation
Breakpoint Behavior
After a breakpoint is signaled (either via the JTAG interface or via the application), each periphery object behaves as described in Table 6-2. Once the chip is halted, it cannot resume.
Table 6-2 Breakpoint behavior Periphery Object XRAM Breakpoint behavior The command FIFO is processed until it is empty. Read data is discarded. Refresh operations continue. All GPIO bits enter tri-state. Data reception continues and data is discarded. Data transmission continues until the TX FIFO empties. Then, based on configuration: Last data value is retransmitted, or A configurable underflow pattern is transmitted.
GPIO RX TX
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Timing Considerations
Figure 6-6 illustrates the timing considerations for the JTAG interface.
Figure 6-6 JTAG Timing
TCLK
TMS, TDI TDO
D0 Q0 tds tdh tdov
D1 Q1 tdoz
Figure 6-7 illustrates the setup and hold time for the PROM interface.
Figure 6-7 PROM Timing
PROM_CLK0
PROM_DATA
D0 tds tdh
D1
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Table 6-3 JTAG & PROM Timing Characteristics Parameter Description Min JTAG Timing tds tdh tdov tdoz Data Setup Data Hold Data Output Valid Data Output Enter Tri-State 2.0 ns 2.0 ns 2.0 ns 0.5 ns (12.0 nsa) 5.5 ns 5.5 ns Max
PROM Timing tds tdh Data Setup Data Hold a. Hold on TDI for access to boundary scan chain only. 5.5 ns 0.0 ns
Supported JTAG and PROM Products JTAG Products
Macraigor Raven Macraigor usb2Sprite
PROM Products
Product Brand Atmel Model Number AT17LV010, AT17LV002, AT17LV040 XC18V01, XC18V02, XC18V04 XC17V01, XC17V02, XC17V04 Frequency 12.5 MHz Density 1 MB, 2 MB, 4 MB 1 MB, 2 MB, 4 MB 1 MB, 2 MB, 4 MB Configuration Serial
Xilinx
33 MHz
Serial or Byte
Xilinx
33 MHz
Serial or Byte
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Chapter 7 Electrical Characteristics
Chapter 7 Electrical Characteristics
Overview
This chapter describes the electrical characteristics of the Arrix family FPOA. Specifically, the following tables are included: "Power Supply Requirements" on page 69, "Absolute Minimum and Maximum Ratings" on page 71, "Operating Conditions" on page 72, and "External Pins" on page 77.
Power Supply Requirements
There are three main voltages that need to be supplied to the Arrix family FPOA: 1.2 V core voltage, 1.8 V RLDRAM voltage, and 2.5 V I/O voltage. All voltages have a 5% tolerance. In addition to the three main supply voltages, there are two reference voltages: 0.9 V for the two RLDRAM interfaces and 1.25 V for the two LVDS TX interfaces.
Table 7-1 Power Supply Requirementsa Voltage VDD XRAM1_VDD_PST XRAM2_VDD_PST XRAM1_VREF XRAM2_VREF GPIO1_VDD_PST GPIO2_VDD_PST RX1_VDD_PST Notes Core supply (106 pins) XRAM HSTL (19 pins) XRAM HSTL (18 pins) XRAM HSTL (3 pins) XRAM HSTL (3 pins) 2.5 v supply for GPIO 1 (12 pins) 2.5 v supply for GPIO 2 (14 pins) LVDS (10 pins) Voltage Supply 1.2 V 5% 1.8 V 5% 1.8 V 5% XRAM1_VDD_PST / 2 1% XRAM1_VDD_PST / 2 1% 2.5 V 5% 2.5 V 5% 2.5 V 5% Current / Power Load 35-40 A b 740 mA 740 mA 100 A 100 A 700 mA 700 mA 100 mA
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Table 7-1 Power Supply Requirementsa (Continued) Voltage RX2_VDD_PST TX1_VDD_PST TX2_VDD_PST TX1_VREF TX2_VREF PROM_VDD_PST JTAG_VDD_PST TPLL1_AVDD TPLL1_AVSS TPLL2_AVDD TPLL2_AVSS CPLL_AVDD CPLL_AVSS Notes LVDS (10 pins) LVDS (15 pins) LVDS (15 pins) Sets common mode output voltage for TX1 driver Sets common mode output voltage for TX2 driver PROM (5 pins) JTAG (2 pins) Analog (2 pins) Analog (2 pins) Core PLL analog supply Voltage Supply 2.5 V 5% 2.5 V 5% 2.5 V 5% 1.25 V 5% 1.25 V 5% 2.5 V 5% 2.5 V 5% 2.5 V 5% 2.5 V 5% 2.5 V 5% Current / Power Load 100 mA 340 mA 340 mA 100 A 100 A 100 mA 80 mA 6 mA 6 mA 6 mA
a. These values are based on pre-silicon estimates. They will be updated once tested with real silicon. b. A large design running at 1 GHz and using every object in the FPOA could in theory draw as much as 50A of core power. In practice, typical designs running at 1GHz tend to max out at 40A. The max amperage decreases with relationship to the number of objects used and at lower core clock frequencies. A design using less than two-thirds of the FPOA objects running at 800 Mhz should not exceed 30A.
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Absolute Minimum and Maximum Ratings
Table 7-2 Absolute Minimum and Maximum Ratings Parameter TJ TS VDD VDD LVCMOS VDD HSTL VDD LVDS VDD PLL Description Junction Temperature Storage Temperature Core Supply Voltage LVCMOS I/O Supply Voltage HSTL I/O Supply Voltage LVDS I/O PLL Analog Supply Voltage Min -40 C -65 C -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V Max +125 Ca 150 C +1.68 V +3.5 V +2.75 V +3.5 V +3.5 V
Note: Long-term exposure to absolute ratings may affect device reliability and permanent damage may occur if ratings are exceeded. The device should be operated under recommended operating conditions. a. Operating life at various frequencies and temperatures: 1 GHz @ 125 C = 4.0 years 1 GHz @ 85 C = 11.4 years 800 MHz @ 125 C = 6.25 years
Operating Conditions
The input waveform illustrated in Figure 7-1 is used for some of the operating conditions specified in Table 7-3:
Figure 7-1 Input Waveform
VDD VIH(min) VIL(max) GND tfall trise
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Table 7-3 Operating Conditions Parameter Description Temperature TJ Junction Temperaturea Core Supply VDD IVDD LVCMOS I/O VDD VIL VIH VOL VOH II IOZ IOL for 8mA drivers IOH for 8mA drivers IOL for 16mA GPIO clock drivers IOH for 16mA GPIO clock drivers CO HSTL I/O VDD VREF VIL VIH I/O Supply Voltage Threshold point Input Low Voltage Input High Voltage VREF + 0.20 V I/O Supply Voltage Input Low Voltage Input High Voltage Output Low voltage Output High voltage Input leakage current @VI=VDD or 0V Tri-state output leakage current @Vo=VDD or 0V Low level output current High level output current Low level output current 10.8 mA 11.5 mA 21.7 mA 18.3 mA 22.8 mA 36.6 mA 1.7 V 10 A 10 A 26.3 mA 37.0 mA 52.5 mA Core Supply Voltage VDD Supply Current 1.14 V 1.2 V 1.26 V -40 C 125 C Min Nom Max
Application dependent. GPIO, PROM, JTAG, PLL Reference Clockb 2.375 V -0.3 V 1.7 V 2.5 V 2.625 V 0.7 V 3.6 V 0.7 V
High level output current
22.9 mA
45.7 mA
73.9 mA
I/O Capacitance XRAM Hardwareb 1.71 V 0.855 V 1.8 V 0.9 V
3.9 pF
1.89 V 0.945 V VREF - 0.20 V
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Table 7-3 Operating Conditions (Continued) Parameter trise tfall VOL VOH IOL IOH CO LVDS I/O VDD VIL VIH RIN CO LVDS I/O VDD trise tfall VCOM VOD IO CO I/O Supply Voltage Output Rise Time Output Fall Time Common Mode Voltage Output Differential Voltage Output Current I/O Capacitance PLL/DLL Analog Supply VAVDD IAVDD PLL/DLL Analog Supply Voltage VAVDD Supply Current 2.25 V 2.5 V 4 mA 2.75 V 6 mA I/O Supply Voltage Differential Input Low Voltage Differential Input High Voltage Differential Input Impedance I/O Capacitance TX Hardwareb 2.375 V 100 ps 100 ps 1.125 V 250 mV 2.0 mA 1.25 V 350 mV 3.5 mA 2.5 V 2.625 V 300 ps 300 ps 1.275 V 400 mV 5.0 mA 2.2 pF Description Output Rise Time Output Fall Time Output low voltage Output high voltage Low level output current High level output current I/O Capacitance RX Hardwareb 2.375 V -0.100 V 0.100 V 80 100 120 2.5 pF 2.5 V 2.625 V VREF + 0.40 V 8 mA -8 mA 3.7 pF Min 550 ps 500 ps Nom 750 ps 750 ps Max 850 ps 900 ps VREF - 0.40 V
a. See Chapter 9: Thermal Considerations. b. Values are specified per pin.
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PLL Power Characteristics
CORE_PLL_AVDD - Isolate 2.5 volts through filter choke. Decouple with 1F capacitor to AGND. TPLL1_VDD - Isolate 2.5 volts through filter choke. Decouple with 1F capacitor to AGND. TPLL2_AVDD - Isolate 2.5 volts through filter choke. Decouple with 1F capacitor to AGND.
Power Sequencing
The power supplies should be sequenced so the 2.5 volt supply (including the analog PLL supplies) comes up first, then the 1.8 volt supply, followed by the 1.2 volt supply. The 2.5 volt supply should lead the 1.8 volt supply by a minimum of 700 mv rise. The 1.8 volt supply should lead the 1.2 volt supply by a minimum of 700 mv rise. TX_VREF should come up after the 2.5 volt supply. XRAM_VREF should come up after the 1.8 volt supply.
Power-up Reset
FPOA Reset should be held active during a power-up until all voltages and clocks are stable plus a minimum of 32 PROM clock (PROM_CLK) cycles.
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Decoupling Capacitors
Recommended for the FPOA: 1.2 V supply Cap. 220F Tantilum - QTY 10 (min) Cap. 10F Ceramic - QTY 10 (min) Cap. 0.10F Ceramic - QTY 40 (min) Cap. 0.01F Ceramic - QTY 40 (min) 1.8 V supply Cap. 220F Tantilum - QTY 6 (min) Cap. 10F Ceramic - QTY 6 (min) Cap. 0.10F Ceramic - QTY 20 (min) Cap. 0.01F Ceramic - QTY 20 (min) 2.5 V supply Cap. 220F Tantilum - QTY 6 (min) Cap. 10F Ceramic - QTY 6 (min) Cap. 0.10F Ceramic - QTY 20 (min) Cap. 0.01F Ceramic - QTY 20 (min) Place 0.10F and 0.01F capacitors as close as possible around the FPOA, intermixing the different voltages.
Current Fluctuations During Initialization
After JTAG or PROM load of the FPOA, the clocks are enabled. However, communication registers are held at initial values. The core supply current will instantaneously jump a certain amount during this period (I2 amps, as specified in Table 7-4). The supply voltage (measured at the chip pin) must not drop more than 20% below nominal. After a configurable number of clock cycles (tid PROM clocks, as specified in Table 7-4), communication registers are released and the chip will start running. The core supply current will increase further (I3 amps, as specified in Table 7-4). At this point, the supply voltage must not drop more than 5% below nominal.
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Figure 7-2 Current Surge at Startup
current
Running application current draw
I3
Initialization current draw
I2
Power-on current draw
time
I1
tid
Clocks enabled Initialization completed
Table 7-4 Current Surge Values Parameter I1 I2 I3 tid Description Power-on current drawa Initialization current drawb Application current drawc Initialization Duration Min 1.0 amps 1.0 amps 0.55 amps Max 3.0 amps 25.0 amps 14 amps
When loading from the PROM, this is a 16-bit value which specifies the number of PROM clocks. This value can be set via a configuration parameter when running the OC (Object Compiler) software.
a. Power-on includes enabling of the PLLs. b. The initialization current surge is dependent on clock frequency and number of objects used by the application. c. The application start up current surge is dependent on clock frequency and application data activity.
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External Pins
Table 7-5 describes the pins associated with core power and core I/O ground. I/O power pins are documented with their corresponding periphery object. For a list of all pins associated with the Arrix family FPOA, see Appendix A: External Pins.
Table 7-5 Voltage and Ground Pins
Pin Number Signal Type Signal Type Core VDD Notes
See below
VDD
PWR
1.2v
Core power supply
The following pins should be connected to the core power supply: H18, H20, H22, J11, J13, J17, J19, J21, J23, K10, K12, K14, K16, K18, K20, K22, L9, L11, L13, L15, L17, L19, L21, L23, L24, M8, M10, M12, M14, M16, M18, M20, M22, N9, N11, N13, N15, N17, N19, N21, N23, N24, P8, P10, P12, P14, P16, P18, P20, P22, R11, R13, R15, R17, R19, R21, T10, T12, T14, T16, T18, T20, U11, U13, U15, U17, U19, U21, V7, V8, V9, V10, V12, V14, V16, V18, V20, V22, W7, W8, W9, W11, W13, W15, W17, W19, W21, W23, Y10, Y12, Y14, Y16, Y18, Y20, AA11, AA13, AA15, AA17, AA19, AB12, AB14, AB16, AB18, AB20, AC17, AC19.
Core & I/O VSS
See below
VSS
GND
0V
Core and I/O ground
The following pins should be connected to ground: B2, B4, B6, B8, B10, B13, B14, B16, B18, B20, B22, B24, B26, B28, D2, D12, D28, F3, F5, F7, F9, F11, F13, F15, F17, F19, F21, F23, G13, G28, H3, H6, H13, H17, H19, H21, H23, J12, J14, J20, J22, J25, J28, K3, K6, K7, K11, K13, K15, K17, K19, K21, K23, L8, L10, L12, L14, L16, L18, L20, L22, L25, L28, M3, M6, M7, M9, M11, M13, M15, M17, M19, M21, M23, N8, N10, N12, N14, N16, N18, N20, N22, N25, N28, P3, P6, P7, P9, P11, P13, P15, P17, P19, P21, P23, R10, R12, R14, R16, R18, R20, R25, R28, T3, T6, T7, T11, T13, T15, T17, T19, T21, T23, T24, U10, U12, U14, U16, U18, U20, U25, U28, V3, V6, V11, V13, V15, V17, V19, V21, V23, W10, W12, W14, W16, W18, W20, W25, W28, Y3, Y11, Y13, Y15, Y17, Y19, Y21, AA10, AA12, AA14, AA16, AA18, AA20, AA22, AA25, AA28, AB3, AB6, AB11, AB13, AB15, AB17, AB19, AC5, AC6, AC12, AC14, AC16, AC20, AC28, AD3, AD11, AE5, AE7, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE28, AF3, AG12, AG28, AJ4, AJ6, AJ8, AJ10, AJ16, AJ18, AJ20, AJ22, AJ24, AJ26, AJ28, AK12.
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Chapter 8 Clock Characteristics
Chapter 8 Clock Characteristics
Core Reference Clock Characteristics
Table 8-1 Core Reference Clock Characteristics Characteristic Reference Clock Frequency Range Reference Clock Duty Cycle Reference Clock Jitter Reference Clock Impedance & Termination Reference Clock Routing Output Clock Multiplier Values Output Clock Frequency Range PLL Lock Time Description 18.75 MHz - 37.5 MHz 20 / 80 200 ps 50 single-ended impedance. No termination. Route as clock signal. Ensure proper spacing away from all other signals. 1, 2, 4, 8, 16, 32 18.75 MHz - 1 GHz 15 s
XRAM Clock Characteristics
Table 8-2 XRAM Clock Characteristics Characteristic Clock Frequency Range Duty Cycle Jitter Impedance & Termination Routing Description 175 MHz - 266 MHz 47 / 53 5% 50 single-ended trace impedance. 50 termination to VTT. Route clock P/N signal pair as a differential route.
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GPIO Clock Characteristics
The GPIO interface can use either an externally-supplied clock (Table 8-3), or it can use the core clock (Table 8-4).
Table 8-3 GPIO Externally-Supplied Clock Characteristics Characteristic Clock Frequency Range Duty Cycle Jitter Impedance & Termination Description 0 - 100 MHz 40 / 60 5% 50 single-ended impedance. No termination.
Table 8-4 GPIO Internally-Supplied Clock Characteristics Characteristic Input Clock Clock Divisor Values Output Clock Frequency Range Output Duty Cycle Jitter Impedance & Termination Other Description Core clock 3 - 511 0 - 100 MHz 45 / 55 5% 50 single-ended impedance. No termination. Note that there is a 16mA drive for the GPIO clock.
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Chapter 8 Clock Characteristics
RX Clock Characteristics
Table 8-5 RX Clock Characteristics Characteristic Clock Frequency Range Duty Cycle Input Jitter Impedance & Termination Description 116 MHz - 500 MHz (DDR) 116 MHz - 640 MHz (SDR) 47 / 53 2% 100 differential impedance. 100 termination built in to the receiver (termination variation is 80 - 120 ).
TX Clock Characteristics
Table 8-6 TX Clock Characteristics Characteristic Reference Clock Frequency Range Reference Clock Duty Cycle Reference Clock Jitter Reference Clock Impedance & Termination Output Clock Multiplier Values Output Clock Frequency Range Output Clock Duty Cycle Output Clock Jitter Output Clock Impedance & Termination PLL Lock Time Description 18.75 MHz - 37.5 MHz 20 / 80 200 ps 50 single-ended impedance. No termination. 1, 2, 4, 8, 16, 32 18.75 MHz - 500 MHz (DDR) 18.75 MHz - 640 MHz (SDR) For PLL multiplier value of 32 - 45 / 55. For all other PLL values - 48 / 52. 50 ps 100 differential impedance. 100 termination between P/N signal pairs. 15 s
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PROM Clock Characteristics
Table 8-7 PROM Clock Characteristics Characteristic Clock Frequency Range Duty Cycle Jitter Impedance & Termination Description 0 - 100 MHz 40 / 60 5% 50 single-ended impedance. No termination.
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Chapter 9 Thermal Considerations
Chapter 9 Thermal Considerations
General Considerations
A heat sink and fan should be selected according to the expected power of the 1.2 V core voltage. Power will depend on the core clock speed and the number of objects used in the design. For maximum power, select a heat sink with a 45 C/watt rating. For a list of recommended heat sinks, see Appendix B: Recommended Heat Sinks.
Junction Temperature
The Arrix family FPOA is rated for a junction temperature (TJ) between -40 C and 125 C. In order to keep the junction temperature in this range, a system design may need to incorporate air flow and/or a heat sink on the device. The type of heat sink required is dependent on many system parameters including the expected power dissipation of the application once it is programmed into the Arrix family FPOA.
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Definition of Terms
When designed into a system, the Arrix family FPOA may or may not need additional thermal enhancements in the form of a passive or active heat sink. The performance and type of heat sink needed (if one is needed) is determined by several operating parameters. These are defined below. TJ: The junction temperature of the semiconductor device, as measured on the die. Measured in C. TC: The case temperature as measured on the top of the package. Measured in C. TA: The ambient temperature of the air immediately above the package and heat sink. Measured in C.
JC: The thermal resistance between the junction and the
case/package of the device. Measured in C/Watt.
CS: The thermal resistance of the adhesive between the case/package and the heat sink. Measured in C/Watt. SA: The thermal resistance between the heat sink and the ambient air. Measured in C/Watt. JA: The thermal resistance between the device junction and the ambient air. JA=JC+CS+SA. Measured in C/Watt.
Air Flow: The air flow in the system, usually measured in linear feet per minute (LFM) or meters per second (m/s). P: The power dissipation of the device. Measured in Watts. Thermal resistance is a measure of how well heat transfers between two entities. A lower value means better heat transfer.
Forced Convection
There are two system conditions for which a heat sink may be required. natural convection (also called still air) and forced convection (by using either an active heat sink or system fan). The calculation for a forced convection heat sink is the most straightforward and will be covered first.
qJA is the main parameter that will define which heat sink should be used. The equation that determines the required JA for a heat sink in a forced
convection environment is as follows:
JA = (TJ - TA) / P
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Chapter 9 Thermal Considerations
JA can be calculated depending on the power that needs to be dissipated, the ambient temperature in the system, and the desired junction temperature. The SA for the heat sink itself can then be calculated from the following equation: SA = JA - JC - CS
For example: Assume an FPOA application that dissipates 25 watts in a system that has an ambient temperature of 40 C. The junction temperature for the FPOA is desired to be 85 C. Calculating JA for this scenario:
JA = (85 - 40) / 25 = 1.8 C/watt
And further calculating SA:
SA = 1.8 - 0.45 - 0.1 = 1.35 C/watt
Using this value, one can find various heat sinks that meet this thermal performance requirement (a heat sink's SA must be equal to or less than the calculated value) at different air flow rates. In this example, the ThermaFlo EH1126 is rated at 0.73 in an air flow of 250 LFM. Since 0.73 is less than the desired 1.35, this heat sink will achieve the desired thermal performance. If the TJ, TA, and power consumption are known, the list of heat sinks in Appendix B can be used to reference heat sink options for that specific design.
Natural Convection
Natural convection occurs when there is no externally induced air flow and heat transfer relies solely on the free buoyant flow of air surrounding the heat sink. Natural convection is often a very demanding system design challenge and is usually interesting when the overall power consumption of the system is low and/or the desired noise output of the system is low. The equation that determines the required JA for a heat sink in a natural convection environment is more complicated because the ambient temperature is also a function of the device power. This means a non-linear equation must be solved in order to arrive at the desired value of JA. This calculation is started by going to the heat sink vendor's web
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site and looking up that heat sink's specifications for temperature rise in C versus heat dissipated in watts. This is often shown in a graphical format. Once the temperature rise is determined, this must be added to the ambient temperature in the equations to determine the desired JA. After this, the calculation is similar to the forced air example. For example: Assume an FPOA application that dissipates 20 watts in a system and has a still-air ambient temperature of 40 C. For this example, assume the allowable junction temperature for the FPOA is 115 C. At this point, a speculative heat sink must be selected so the ambient temperature rise can be determined as a function of the power. In this case, a ThermaFlo E3180 is chosen and by looking at the temperature rise versus power chart, a 24 C value is found for 20 Watts dissipated. This is added to the ambient temperature and JA is calculated. For this scenario:
JA = (115 - (40 + 24)) / 20 = 2.55 C/Watt
And further calculating SA:
SA = 2.55 - 0.45 - 0.1 = 1.8 C/Watt
Checking the ThermaFlo heat sink's rated SA for 20 watts, we find a value of 1.35 C/watt. Since this value is lower (better) than 1.8, we know this heat sink will work in this example. Natural convection is a difficult system environment in which to design. Since the heat dissipation performance of the heat sink is a function of the heat sink surface area, often a very large and heavy heat sink is required. Many times, the trade-off of adding a system fan, even with the added expense, is much more cost-effective than the natural convection approach. If the TJ, TA, and power consumption are known, the list of heat sinks in Appendix B can be used to reference heat sink options for that specific design.
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Chapter 10 Packaging Information
Chapter 10 Packaging Information
Overview
The Arrix product family package is an 896-pin high-performance Flip-Chip Ball Grid Array (HFCBGA). This package provides a large number of solder-ball interconnects and excellent thermal characteristics with a top-mounted heat spreader.
Package Dimensions
The following diagrams detail the dimensions of the Arrix product family FPOA. Values for each symbol are specified in Table 10-1 on page 89.
Figure 10-1 Package Dimensions - Top View
-A- D aaa
Pin #1 Corner
-B-
E
aaa
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Figure 10-2 Package Dimensions - Side View
"A" ccc C A A1 A2 -C-
1
ddd C
Detail "A"
Figure 10-3 Package Dimensions - Bottom View
D D1 Pin #1 Corner
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
b
e
NOTE: This is a top-down view of the ball pattern
E E1 AH AJ AK 1 2 3
eee fff
M M
CAB C
b
2
"B"
Detail "B"
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1 2
Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. Dimension b is measured at the maximum solder ball diameter, parallel to primary Datum C.
3. There should be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 4. The tilt of the heat sink should be within 0.254 mm (vertical position).
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Chapter 10 Packaging Information
Table 10-1 Package Dimensions Symbol A A1 A2 D D1 E E1 b e aaa ccc ddd eee fff Description Distance from the seating plane to the highest point of the package. Ball height. Thickness of the package body, exclusive of the ball height. Length of the body measured at the outermost extremes. Distance between centerlines of the first and last ball on the long axis of the package. Width of the body measured at the outermost extremes. Distance between centerlines of the first and last ball on the short axis of the package. Diameter of a single ball. Centerline to centerline spacing of the ball. Bilateral profile tolerance zone that controls the size and orientation of the sides of the carrier body. Bilateral tolerance zone for parallelism of the lid surface with respect to the seating plane (Datum C). Unidirectional profile tolerance zone that extends upward from the seating plane (Datum C). Tolerance of position that controls the matrix pattern of balls as a whole with respect to Datums A and B. Tolerance of position that controls the relationship of the balls with respect to each other within the pattern. Dimensions in millimeters Min 2.60 0.40 2.20 30.80 --30.80 --0.50 ------------Nom 3.00 0.50 2.50 31.00 29.00 31.00 29.00 0.60 1.00 0.20 0.25 0.20 0.30 0.10 Max 3.40 0.60 2.80 31.20 --31.20 --0.70 -------------
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Ball Pattern
The FPOA ball pattern is a 30 x 30 array of balls. For a description of each pin sorted by ball position, see Appendix A: External Pins. For a description of each pin associated with its respective component, refer to the following chapters: Chapter 2: XRAM Hardware This chapter describes all pins associated with the XRAM controller. Chapter 3: GPIO Hardware This chapter describes all pins associated with the GPIO interface. Chapter 4: RX Hardware This chapter describes all pins associated with the RX interface. Chapter 5: TX Hardware This chapter describes all pins associated with the TX interface. Chapter 6: Initialization and Control This chapter describes all pins associated with the initialization and control periphery objects (JTAG interface, PROM interface, PLL, Debug, etc.). Chapter 7: Electrical Characteristics This chapter describes all pins associated with power and ground.
Recommended PC Board Characteristics
Characteristic Layers Signal Layers 1.2 volt power supplies 1.8 volt power supplies 2.5 volt power supplies Ground Layers Analog Ground Layers Impedance Characteristics
Value 12 6 1 1 1 2 1 Single ended: 50 Differential pairs: 100
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Appendix A: External Pins
Appendix A: External Pins
This chapter describes each pin (sorted by ball position) on the Arrix family FPOA shown in Figure 11-1.
Figure 11-1 Ball Pattern for FPOA (Top-down View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
For a description of each pin sorted by hardware type, refer to the chapter for that particular hardware.
Table 11-1 External Pins
Pin Number
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10
Signal
None GPIO1_15 GPIO1_18 GPIO1_23 GPIO1_29 GPIO1_28 GPIO1_36 GPIO1_35 GPIO1_38 GPIO1_42
Type
N/A I/O I/O I/O I/O I/O I/O I/O I/O I/O
Signal Type
N/A LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
Description
No ball GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit
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Table 11-1 External Pins (Continued)
Pin Number
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13
Signal
GPIO1_46 XRAM1_DQS2_P XRAM1_VDD_PST XRAM1_DATA_0 XRAM1_DATA_5 XRAM1_DATA_11 XRAM1_DATA_13 XRAM1_DATA_19 XRAM1_DATA_20 XRAM1_DATA_24 XRAM1_DATA_27 XRAM1_DATA_28 XRAM1_CNTL_0 XRAM1_ADDR_0 XRAM1_ADDR_2 XRAM1_ADDR_6 XRAM1_ADDR_9 XRAM1_ADDR_12 XRAM1_ADDR_20 None GPIO1_14 VSS GPIO1_17 VSS GPIO1_22 VSS GPIO1_30 VSS GPIO1_37 VSS GPIO1_47 XRAM1_DQS2_N VSS
Type
I/O I PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O N/A I/O GND I/O GND I/O GND I/O GND I/O GND I/O I GND
Signal Type
LVCMOS HSTL 1.8V HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL N/A LVCMOS 0V LVCMOS 0V LVCMOS 0V LVCMOS 0V LVCMOS 0V LVCMOS HSTL 0V
Description
GPIO data bit XRAM Differential Input strobe (bits 18-26) Connect to XRAM I/O Power (1.8V) XRAM Data bit (LSB) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Control bit XRAM Address bit (LSB) XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit (MSB) No ball GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit XRAM Differential Input strobe (bits 18-26) Core and I/O ground
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16
Signal
VSS XRAM1_DK0_N VSS XRAM1_DATA_12 VSS XRAM1_DATA_25 VSS XRAM1_DATA_31 VSS XRAM1_CNTL_2 VSS XRAM1_ADDR_1 VSS XRAM1_ADDR_8 VSS XRAM1_ADDR_19 PROM_VDD_PST GPIO1_6 GPIO1_5 GPIO1_VDD_PST GPIO1_16 GPIO1_VDD_PST GPIO1_21 GPIO1_VDD_PST GPIO1_27 GPIO1_VDD_PST GPIO1_41 XRAM1_DQS0_P XRAM1_VDD_PST XRAM1_DQS3_P XRAM1_DATA_4 XRAM1_DK0_P XRAM1_DK1_N
Type
GND O GND I/O GND I/O GND I/O GND O GND O GND O GND O PWR I/O I/O PWR I/O PWR I/O PWR I/O PWR I/O I PWR I I/O O O
Signal Type
0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 2.5V LVCMOS LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V LVCMOS HSTL 1.8V HSTL HSTL HSTL HSTL
Description
Core and I/O ground XRAM Differential Output clock (bits 0-8) Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Control bit Core and I/O ground XRAM Address bit Core and I/O ground XRAM Address bit Core and I/O ground XRAM Address bit Connect to 2.5V GPIO data bit GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit XRAM Differential Input strobe (bits 0-8, DVLD) Connect to XRAM I/O Power (1.8V) XRAM Differential Input strobe (bits 27-35) XRAM Data bit XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 9-17)
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18
Signal
XRAM1_VDD_PST XRAM1_DATA_18 XRAM1_VDD_PST XRAM1_DK2_P XRAM1_VDD_PST XRAM1_DATA_35 XRAM1_VDD_PST XRAM1_CLK_N XRAM1_VDD_PST XRAM1_ADDR_10 XRAM1_VDD_PST XRAM1_ADDR_18 XRAM1_VDD_PST PROM_DATA_1 GPIO1_0 VSS GPIO1_13 GPIO1_12 GPIO1_19 GPIO1_20 GPIO1_CLK GPIO1_31 GPIO1_39 GPIO1_45 XRAM1_DQS0_N VSS XRAM1_DQS3_N XRAM1_DATA_3 XRAM1_VDD_PST XRAM1_DK1_P XRAM1_DATA_16 XRAM1_DATA_23
Type
PWR I/O PWR O PWR I/O PWR O PWR O PWR O PWR I I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I GND I I/O PWR O I/O I/O
Signal Type
1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V LVCMOS LVCMOS 0V LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS HSTL 0V HSTL HSTL 1.8V HSTL HSTL HSTL
Description
Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Differential Output clock (bits 18-26) Connect to XRAM I/O Power (1.8V) XRAM Data bit (MSB) Connect to XRAM I/O Power (1.8V) XRAM Differential output command clock Connect to XRAM I/O Power (1.8V) XRAM Address bit Connect to XRAM I/O Power (1.8V) XRAM Address bit Connect to XRAM I/O Power (1.8V) PROM Data bit GPIO data bit Core and I/O ground GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO clocka GPIO data bit GPIO data bit GPIO data bit XRAM Differential Input strobe (bits 0-8, DVLD) Core and I/O ground XRAM Differential Input strobe (bits 27-35) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Differential Output clock (bits 9-17) XRAM Data bit XRAM Data bit
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15
Signal
XRAM1_DK3_N XRAM1_DK2_N XRAM1_DATA_33 XRAM1_DATA_34 XRAM1_CNTL_1 XRAM1_CLK_P XRAM1_ADDR_7 XRAM1_ADDR_11 XRAM1_ADDR_13 VSS PROM_DATA_2 PROM_VDD_PST GPIO1_1 GPIO1_VDD_PST GPIO1_2 GPIO1_7 GPIO1_9 GPIO1_26 GPIO1_24 GPIO1_32 GPIO1_34 GPIO1_44 XRAM1_VDD_PST XRAM1_DQS1_P XRAM1_VDD_PST XRAM1_DATA_2 XRAM1_DVLD
Type
O O I/O I/O O O O O O GND I PWR I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O PWR I PWR I/O I
Signal Type
HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL 0V LVCMOS 2.5V LVCMOS 2.5V LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 1.8V HSTL 1.8V HSTL HSTL
Description
XRAM Differential Output clock (bits 27-35) XRAM Differential Output clock (bits 18-26) XRAM Data bit XRAM Data bit XRAM Control bit XRAM Command clock XRAM Address bit XRAM Address bit XRAM Address bit Core and I/O ground PROM Data bit Connect to 2.5V GPIO data bit Connect to GPIO power (2.5V) GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit Connect to XRAM I/O Power (1.8V) XRAM Differential Input strobe (bits 9-17) Connect to XRAM I/O Power (1.8V) XRAM Data bit XRAM Data Valid Input This pin should come from the RLDRAM devices associated with XRAM_DATA[8:0]. XRAM Data bit XRAM Data bit XRAM Data bit XRAM Differential Output clock (bits 27-35)
E16 E17 E18 E19
XRAM1_DATA_10 XRAM1_DATA_15 XRAM1_DATA_22 XRAM1_DK3_P
I/O I/O I/O O
HSTL HSTL HSTL HSTL
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Table 11-1 External Pins (Continued)
Pin Number
E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22
Signal
XRAM1_DATA_30 XRAM1_DATA_32 XRAM1_BANK_2 XRAM1_ADDR_5 XRAM1_ADDR_4 XRAM1_ADDR_16 XRAM1_ADDR_14 XRAM1_ADDR_17 XRAM1_VDD_PST PROM_DATA_3 PROM_DATA_0 TX1_DATA_15_N TX1_DATA_15_P VSS GPIO1_4 VSS GPIO1_8 VSS GPIO1_25 VSS GPIO1_40 VSS XRAM1_DQS1_N VSS XRAM1_DATA_1 VSS XRAM1_DATA_9 VSS XRAM1_DATA_21 VSS XRAM1_DATA_29 VSS XRAM1_BANK_1
Type
I/O I/O O O O O O O PWR I I O O GND I/O GND I/O GND I/O GND I/O GND I GND I/O GND I/O GND I/O GND I/O GND O
Signal Type
HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL 1.8V LVCMOS LVCMOS LVDS/HSTL LVDS/HSTL 0V LVCMOS 0V LVCMOS 0V LVCMOS 0V LVCMOS 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL
Description
XRAM Data bit XRAM Data bit XRAM Bank bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit Connect to XRAM I/O Power (1.8V) PROM Data bit PROM Data bit (LSB) Transmit Data bit Transmit Data bit (MSB) Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground XRAM Differential Input strobe (bits 9-17) Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Bank bit
96
Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
F23 F24 F25 F26 F27 F28 F29
Signal
VSS XRAM1_ADDR_3 PROM_VDD_PST XRAM1_ADDR_15 PROM_CLKO PROM_DATA_4 PROM_CLKDIV
Type
GND O PWR O O I I
Signal Type
0V HSTL 2.5V HSTL LVCMOS LVCMOS LVCMOS
Description
Core and I/O ground XRAM Address bit Connect to 2.5V XRAM Address bit PROM Clock Output PROM Data bit PROM Clock Divider Input 0 = Divide by 2 1 = Divide by 4 Connect to 2.5V LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) No Connect Connect to GPIO power (2.5V) Core and I/O ground Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Bank bit Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V)
F30 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23
PROM_VDD_PST TX1_VDD_PST TX1_DATA_14_N TX1_DATA_14_P TX1_VDD_PST GPIO1_3 GPIO1_VDD_PST GPIO1_11 GPIO1_VDD_PST GPIO1_33 GPIO1_VDD_PST NC12 GPIO1_VDD_PST VSS XRAM1_VDD_PST XRAM1_DATA_7 XRAM1_VDD_PST XRAM1_DATA_14 XRAM1_VDD_PST XRAM1_DATA_26 XRAM1_VDD_PST XRAM1_BANK_0 XRAM1_VDD_PST XRAM1_VDD_PST
PWR PWR O O PWR I/O PWR I/O PWR I/O PWR N/A PWR GND PWR I/O PWR I/O PWR I/O PWR O PWR PWR
2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V N/A 2.5V 0V 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V 1.8V
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
G24 G25 G26 G27 G28 G29 G30 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26
Signal
PROM_VDD_PST PROM_CEN PROM_DATA_5 PROM_CLK VSS RX2_DATA_15_N RX2_DATA_15_P TX1_DATA_12_N TX1_DATA_12_P VSS TX1_DATA_13_N TX1_DATA_13_P VSS GPIO1_10 GPIO1_VDD_PST GPIO1_VDD_PST GPIO1_43 NC13 GPIO1_VDD_PST VSS XRAM1_DATA_6 XRAM1_DATA_8 XRAM1_DATA_17 VSS VDD VSS VDD VSS VDD VSS PROM_DISABLE PROM_OE PROM_DATA_6
Type
PWR O I I GND I I O O GND O O GND I/O PWR PWR I/O N/A PWR GND I/O I/O I/O GND PWR GND PWR GND PWR GND I O I
Signal Type
2.5V LVCMOS LVCMOS LVCMOS 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V LVCMOS 2.5V 2.5V LVCMOS N/A 2.5V 0V HSTL HSTL HSTL 0V 1.2v 0V 1.2v 0V 1.2v 0V LVCMOS LVCMOS LVCMOS
Description
Connect to 2.5V PROM Chip Enable (low active) PROM Data bit PROM Clock Input Core and I/O ground Receive Data bit Receive Data bit (MSB) Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Core and I/O ground GPIO data bit Connect to GPIO power (2.5V) Connect to GPIO power (2.5V) GPIO data bit No Connect Connect to GPIO power (2.5V) Core and I/O ground XRAM Data bit XRAM Data bit XRAM Data bit Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground PROM Disable Input PROM Output Enable PROM Data bit
98
Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
H27 H28 H29 H30 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10
Signal
PROM_DATA_7 RX2_DATA_13_P RX2_DATA_13_N RX2_VDD_PST TX1_VDD_PST TX1_DATA_10_P TX1_DATA_10_N TX1_VDD_PST TX1_DATA_11_N TX1_DATA_11_P TX1_VDD_PST TPLL1_CAP TPLL1_REF TPLL1_AVSS
Type
I I I PWR PWR O O PWR O O PWR I I GND
Signal Type
LVCMOS LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V Analog LVCMOS Analog
Description
PROM Data bit (MSB) Receive Data bit Receive Data bit Connect to 2.5V LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Do not connect 18.75 - 37.5Mhz reference clock input for Transmit PLL Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information. Core power supply Core and I/O ground Core power supply Core and I/O ground Connect to XRAM reference voltage (0.9V) Connect to XRAM reference voltage (0.9V) Core power supply Connect to XRAM reference voltage (0.9V) Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply PROM Serial/Parallel mode select 0 = 8-bit connection 1 = 1-bit connection Core and I/O ground Receive Data bit
J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24
VDD VSS VDD VSS XRAM1_VREF1 XRAM1_VREF2 VDD XRAM1_VREF3 VDD VSS VDD VSS VDD PROM_SERIAL
PWR GND PWR GND I I PWR I PWR GND PWR GND PWR I
1.2v 0V 1.2v 0V Analog Analog 1.2v Analog 1.2v 0V 1.2v 0V 1.2v LVCMOS
J25 J26
VSS RX2_DATA_14_P
GND I
0V LVDS/HSTL
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
J27 J28 J29 J30 K01 K02 K03 K04 K05 K06 K07 K08 K09
Signal
RX2_DATA_14_N VSS RX2_DATA_10_P RX2_DATA_10_N TX1_DATA_8_P TX1_DATA_8_N VSS TX1_DATA_9_N TX1_DATA_9_P VSS VSS NC6 TPLL1_AVDD
Type
I GND I I O O GND O O GND GND N/A PWR
Signal Type
LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V 0V N/A Analog
Description
Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Core and I/O ground Core and I/O ground No Connect Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V
K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27
VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS RX2_VDD_PST RX2_DATA_12_N RX2_DATA_12_P RX2_VDD_PST
PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR I I PWR
1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 2.5V LVDS/HSTL LVDS/HSTL 2.5V
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
www..com
Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
K28 K29 K30 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30
Signal
RX2_DATA_11_N RX2_DATA_11_P RX2_VDD_PST TX1_VDD_PST TX1_DATA_7_N TX1_DATA_7_P TX1_VDD_PST TX1_CNTL_N TX1_CNTL_P TX1_VDD_PST VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS RX2_DATA_9_P RX2_DATA_9_N VSS RX2_DATA_8_P RX2_DATA_8_N
Type
I I PWR PWR O O PWR O O PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR PWR GND I I GND I I
Signal Type
LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 1.2v 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL
Description
Receive Data bit Receive Data bit Connect to 2.5V LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Transmit Control bit Transmit Control bit LVDS 2.5V Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core power supply Core and I/O ground Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 N01 N02 N03
Signal
TX1_DATA_5_N TX1_DATA_5_P VSS TX1_DATA_6_N TX1_DATA_6_P VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS RX2_VDD_PST RX2_CNTL_P RX2_CNTL_N RX2_VDD_PST RX2_DATA_7_N RX2_DATA_7_P RX2_VDD_PST TX1_VDD_PST TX1_CLK1_N TX1_CLK1_P
Type
O O GND O O GND GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR I I PWR I I PWR PWR O O
Signal Type
LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL
Description
Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Core and I/O ground Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Connect to 2.5V Receive Control bit Receive Control bit Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V LVDS 2.5V Transmit Clock Transmit Clock
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 P01 P02 P03 P04 P05 P06
Signal
TX1_VDD_PST TX1_DATA_4_N TX1_DATA_4_P TX1_VDD_PST VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS RX2_DATA_6_P RX2_DATA_6_N VSS RX2_DATA_5_N RX2_DATA_5_P TX1_DATA_2_N TX1_DATA_2_P VSS TX1_DATA_3_N TX1_DATA_3_P VSS
Type
PWR O O PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR PWR GND I I GND I I O O GND O O GND
Signal Type
2.5V LVDS/HSTL LVDS/HSTL 2.5V 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 1.2v 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V
Description
LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core power supply Core and I/O ground Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Core and I/O ground
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R01 R02 R03 R04 R05 R06 R07 R08 R09
Signal
VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS RX2_VDD_PST RX2_CLK1_P RX2_CLK1_N RX2_VDD_PST RX2_DATA_4_N RX2_DATA_4_P RX2_VDD_PST TX1_VDD_PST TX1_DATA_0_P TX1_DATA_0_N TX1_VDD_PST TX1_DATA_1_N TX1_DATA_1_P TX1_VDD_PST TX1_VDD_PST NC8
Type
GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR I I PWR I I PWR PWR O O PWR O O PWR PWR N/A
Signal Type
0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V N/A
Description
Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Connect to 2.5V Receive Clock Receive Clock Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V LVDS 2.5V Transmit Data bit Transmit Data bit (LSB) LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V LVDS 2.5V No Connect
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
www..com
Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12
Signal
VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC17 NC10 RX2_VDD_PST VSS RX2_DATA_3_P RX2_DATA_3_N VSS RX2_DATA_2_N RX2_DATA_2_P RX1_DATA_0_P RX1_DATA_0_N VSS TX1_TEST_N TX1_TEST_P VSS VSS NC16 NC1 VDD VSS VDD
Type
GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR N/A N/A PWR GND I I GND I I I I GND O O GND GND N/A N/A PWR GND PWR
Signal Type
0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v N/A N/A 2.5V 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V 0V N/A N/A 1.2v 0V 1.2v
Description
Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply No Connect No Connect Connect to 2.5V Core and I/O ground Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Receive Data bit Receive Data bit (LSB) Core and I/O ground Production test pin - do not connect Production test pin - do not connect Core and I/O Ground Core and I/O Ground No Connect No Connect Core power supply Core and I/O ground Core power supply
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14
Signal
VSS VDD VSS VDD VSS VDD VSS VDD VSS NC11 VSS VSS RX2_DATA_1_P RX2_DATA_1_N RX2_VDD_PST RX2_DATA_0_N RX2_DATA_0_P RX2_VDD_PST RX1_VDD_PST RX1_DATA_1_N RX1_DATA_1_P RX1_VDD_PST RX1_DATA_2_N RX1_DATA_2_P NC2 NC9 TX1_VREF VSS VDD VSS VDD VSS
Type
GND PWR GND PWR GND PWR GND PWR GND N/A GND GND I I PWR I I PWR PWR I I PWR I I N/A N/A I GND PWR GND PWR GND
Signal Type
0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V N/A 0V 0V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL N/A N/A 1.2V Analog 0V 1.2v 0V 1.2v 0V
Description
Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground No Connect Core and I/O ground Core and I/O ground Receive Data bit Receive Data bit Connect to 2.5V Receive Data bit (LSB) Receive Data bit Connect to 2.5V Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V Receive Data bit Receive Data bit No Connect No Connect LVDS TX1 Analog 1.2V common mode voltage reference Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
www..com
Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16
Signal
VDD VSS VDD VSS VDD VSS VDD NC3 TX2_VREF NC4 VSS TX2_DATA_0_P TX2_DATA_0_N VSS TX2_TEST_N TX2_TEST_P RX1_DATA_3_P RX1_DATA_3_N VSS RX1_CLK1_P RX1_CLK1_N VSS VDD VDD VDD VDD VSS VDD VSS VDD VSS VDD
Type
PWR GND PWR GND PWR GND PWR N/A I N/A GND O O GND O O I I GND I I GND PWR PWR PWR PWR GND PWR GND PWR GND PWR
Signal Type
1.2v 0V 1.2v 0V 1.2v 0V 1.2v N/A Analog N/A 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V 1.2v 1.2v 1.2v 1.2v 0V 1.2v 0V 1.2v 0V 1.2v
Description
Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply No Connect LVDS TX2 Analog 1.2V common mode voltage reference No Connect Core and I/O ground Transmit Data bit Transmit Data bit (LSB) Core and I/O ground Production test pin - do not connect Production test pin - do not connect Receive Data bit Receive Data bit Core and I/O ground Receive Clock Receive Clock Core and I/O ground Core power supply Core power supply Core power supply Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply
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Arrix Family Data Sheet
Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19
Signal
VSS VDD VSS VDD VSS VDD VSS TX2_VDD_PST TX2_DATA_2_P TX2_DATA_2_N TX2_VDD_PST TX2_DATA_1_N TX2_DATA_1_P TX2_VDD_PST RX1_VDD_PST RX1_DATA_4_N RX1_DATA_4_P RX1_VDD_PST RX1_DATA_5_P RX1_DATA_5_N VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD
Type
GND PWR GND PWR GND PWR GND PWR O O PWR O O PWR PWR I I PWR I I PWR PWR PWR GND PWR GND PWR GND PWR GND PWR GND PWR
Signal Type
0V 1.2v 0V 1.2v 0V 1.2v 0V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 1.2v 1.2v 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v
Description
Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V Receive Data bit Receive Data bit Core power supply Core power supply Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08
Signal
VSS VDD NC7 VDD TX2_VDD_PST VSS TX2_CLK1_P TX2_CLK1_N VSS TX2_DATA_3_P TX2_DATA_3_N RX1_DATA_6_N RX1_DATA_6_P VSS RX1_DATA_7_N RX1_DATA_7_P CPLL_CAP CLOCK_P CPLL_AVSS
Type
GND PWR N/A PWR PWR GND O O GND O O I I GND I I I I GND
Signal Type
0V 1.2v N/A 1.2v 2.5V 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL Analog LVDS Analog
Description
Core and I/O ground Core power supply No Connect Core power supply LVDS 2.5V Core and I/O ground Transmit Clock Transmit Clock Core and I/O ground Transmit Data bit Transmit Data bit Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Do not connect Core clock bypass input Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information. Connect to GPIO power (2.5V) Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply
Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
GPIO2_VDD_PST VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD
PWR PWR GND PWR GND PWR GND PWR GND PWR GND PWR
2.5V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
Y21 Y22
Signal
VSS TPLL2_AVSS
Type
GND GND
Signal Type
0V Analog
Description
Core and I/O ground Connect to Analog Ground See "PLL Power Characteristics" on page 74 for more information. Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V Receive Control bit Receive Control bit Core clock bypass input Connect to Analog 2.5V See "PLL Power Characteristics" on page 74 for more information. 18.75 - 37.5 MHz reference clock input for Core PLL Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply
Y23
TPLL2_AVDD
PWR
Analog
Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08
TX2_VDD_PST TX2_DATA_5_P TX2_DATA_5_N TX2_VDD_PST TX2_DATA_4_P TX2_DATA_4_N TX2_VDD_PST RX1_VDD_PST RX1_DATA_8_N RX1_DATA_8_P RX1_VDD_PST RX1_CNTL_N RX1_CNTL_P CLOCK_N CPLL_AVDD
PWR O O PWR O O PWR PWR I I PWR I I I PWR
2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL LVDS Analog
AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19
CPLL_REF VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD
I GND PWR GND PWR GND PWR GND PWR GND PWR
LVCMOS 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21
Signal
VSS JTAG_VDD_PST VSS TPLL2_CAP TRSTn VSS TX2_DATA_7_N TX2_DATA_7_P VSS TX2_DATA_6_P TX2_DATA_6_N RX1_DATA_9_N RX1_DATA_9_P VSS RX1_DATA_11_N RX1_DATA_11_P VSS NC5 GPIO2_20 GPIO2_18 GPIO2_VDD_PST VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD JTAG_VDD_PST
Type
GND PWR GND I I GND O O GND O O I I GND I I GND N/A I/O I/O PWR GND PWR GND PWR GND PWR GND PWR GND PWR PWR
Signal Type
0V 2.5V 0V Analog LVCMOS 0V LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 0V N/A LVCMOS LVCMOS 2.5V 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 0V 1.2v 2.5V
Description
Core and I/O ground Connect to 2.5V Core and I/O ground Do not connect JTAG Test Reset (low active) This input has a built-in pullup resistor. Core and I/O ground Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Core and I/O ground No Connect GPIO data bit GPIO data bit Connect to GPIO power (2.5V) Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Core and I/O ground Core power supply Connect to 2.5V
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
AB22 AB23 AB24
Signal
TMS TDO TCLK
Type
I O I
Signal Type
LVCMOS LVCMOS LVCMOS
Description
JTAG Test Mode Select This input has a built-in pullup resistor. JTAG Test Data Output JTAG Test Clock Input This input has a built-in pullup resistor. Transmit Data bit Transmit Data bit LVDS 2.5V Transmit Control bit Transmit Control bit LVDS 2.5V Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V Core and I/O ground Core and I/O ground GPIO data bit GPIO data bit GPIO data bit Connect to GPIO power (2.5V) No Connect Core and I/O ground No Connect Core and I/O ground Connect to XRAM reference voltage (0.9V) Core and I/O ground Core power supply Connect to XRAM reference voltage (0.9V) Core power supply Core and I/O ground 18.75 - 37.5Mhz reference clock input for Transmit PLL FPOA Reset (low active)
AB25 AB26 AB27 AB28 AB29 AB30 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22
TX2_DATA_8_N TX2_DATA_8_P TX2_VDD_PST TX2_CNTL_P TX2_CNTL_N TX2_VDD_PST RX1_VDD_PST RX1_DATA_10_P RX1_DATA_10_N RX1_VDD_PST VSS VSS GPIO2_14 GPIO2_21 GPIO2_19 GPIO2_VDD_PST NC15 VSS NC14 VSS XRAM2_VREF1 VSS VDD XRAM2_VREF2 VDD VSS TPLL2_REF RESETn
O O PWR O O PWR PWR I I PWR GND GND I/O I/O I/O PWR N/A GND N/A GND I GND PWR I PWR GND I I
LVDS/HSTL LVDS/HSTL 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V 0V 0V LVCMOS LVCMOS LVCMOS 2.5V N/A 0V N/A 0V Analog 0V 1.2v Analog 1.2v 0V LVCMOS LVCMOS
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23
Signal
TDI TESTMODE XRAM2_ADDR_10 TX2_DATA_10_P TX2_DATA_10_N VSS TX2_DATA_9_N TX2_DATA_9_P RX1_DATA_12_N RX1_DATA_12_P VSS RX1_DATA_13_N RX1_DATA_13_P GPIO2_VDD_PST GPIO2_15 GPIO2_VDD_PST GPIO2_28 GPIO2_VDD_PST VSS XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_DATA_9 XRAM2_VDD_PST XRAM2_DATA_16 XRAM2_VDD_PST XRAM2_VREF3 XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_VDD_PST XRAM2_ADDR_4
Type
I I O O O GND O O I I GND I I PWR I/O PWR I/O PWR GND PWR PWR PWR I/O PWR I/O PWR I PWR PWR PWR O
Signal Type
LVCMOS LVCMOS HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL 2.5V LVCMOS 2.5V LVCMOS 2.5V 0V 1.8V 1.8V 1.8V HSTL 1.8V HSTL 1.8V Analog 1.8V 1.8V 1.8V HSTL
Description
JTAG Test Data Input This input has a built-in pullup resistor. Connect to ground This input has a built-in pulldown resistor. XRAM Address bit Transmit Data bit Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Receive Data bit Receive Data bit Core and I/O ground Receive Data bit Receive Data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) Core and I/O ground Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) Connect to XRAM reference voltage (0.9V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) Connect to XRAM I/O Power (1.8V) XRAM Address bit
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
AD24 AD25 AD26 AD27 AD28 AD29 AD30 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Signal
XRAM2_VDD_PST XRAM2_ADDR_11 TX2_VDD_PST TX2_VDD_PST TX2_DATA_11_N TX2_DATA_11_P TX2_VDD_PST RX1_VDD_PST RX1_DATA_14_N RX1_DATA_14_P RX1_VDD_PST VSS GPIO2_VDD_PST VSS GPIO2_22 VSS GPIO2_35 VSS XRAM2_DQS0_P VSS XRAM2_DATA_6 VSS XRAM2_DATA_13 VSS XRAM2_DATA_20 VSS XRAM2_DK2_P VSS XRAM2_DATA_34 VSS XRAM2_ADDR_3 VSS TX2_DATA_12_P
Type
PWR O PWR PWR O O PWR PWR I I PWR GND PWR GND I/O GND I/O GND I GND I/O GND I/O GND I/O GND O GND I/O GND O GND O
Signal Type
1.8V HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V 2.5V LVDS/HSTL LVDS/HSTL 2.5V 0V 2.5V 0V LVCMOS 0V LVCMOS 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V LVDS/HSTL
Description
Connect to XRAM I/O Power (1.8V) XRAM Address bit LVDS 2.5V LVDS 2.5V Transmit Data bit Transmit Data bit LVDS 2.5V Connect to 2.5V Receive Data bit Receive Data bit Connect to 2.5V Core and I/O ground Connect to GPIO power (2.5V) Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground XRAM Differential Input strobe (bits 0-8, DVLD) Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Differential Output clock (bits 18-26) Core and I/O ground XRAM Data bit Core and I/O ground XRAM Address bit Core and I/O ground Transmit Data bit
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
AE27 AE28 AE29 AE30 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29
Signal
TX2_DATA_12_N VSS TX2_DATA_13_P TX2_DATA_13_N RX1_DATA_15_N RX1_DATA_15_P VSS GPIO2_VDD_PST GPIO2_11 GPIO2_16 GPIO2_VDD_PST GPIO2_23 GPIO2_37 GPIO2_36 GPIO2_45 XRAM2_DQS0_N XRAM2_DQS2_P XRAM2_DATA_0 XRAM2_DATA_7 XRAM2_DATA_14 XRAM2_DATA_17 XRAM2_DATA_21 XRAM2_DATA_22 XRAM2_DK2_N XRAM2_DATA_28 XRAM2_DATA_35 XRAM2_ADDR_0 XRAM2_ADDR_5 XRAM2_ADDR_6 XRAM2_ADDR_12 XRAM2_ADDR_19 TX2_DATA_14_P TX2_DATA_14_N
Type
O GND O O I I GND PWR I/O I/O PWR I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O O I/O I/O O O O O O O O
Signal Type
LVDS/HSTL 0V LVDS/HSTL LVDS/HSTL LVDS/HSTL LVDS/HSTL 0V 2.5V LVCMOS LVCMOS 2.5V LVCMOS LVCMOS LVCMOS LVCMOS HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL LVDS/HSTL LVDS/HSTL
Description
Transmit Data bit Core and I/O ground Transmit Data bit Transmit Data bit Receive Data bit Receive Data bit (MSB) Core and I/O ground Connect to GPIO power (2.5V) GPIO data bit GPIO data bit Connect to GPIO power (2.5V) GPIO data bit GPIO data bit GPIO data bit GPIO data bit XRAM Differential Input strobe (bits 0-8, DVLD) XRAM Differential Input strobe (bits 18-26) XRAM Data bit (LSB) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Differential Output clock (bits 18-26) XRAM Data bit XRAM Data bit (MSB) XRAM Address bit (LSB) XRAM Address bit XRAM Address bit XRAM Address bit XRAM Address bit Transmit Data bit Transmit Data bit
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
AF30 AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15
Signal
TX2_VDD_PST GPIO2_0 GPIO2_8 GPIO2_3 GPIO2_9 GPIO2_12 GPIO2_17 GPIO2_CLK GPIO2_29 GPIO2_38 GPIO2_39 GPIO2_46 VSS XRAM2_DQS2_N XRAM2_DATA_1 XRAM2_DVLD
Type
PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I I/O I
Signal Type
2.5V LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 0V HSTL HSTL HSTL
Description
LVDS 2.5V GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO clocka GPIO data bit GPIO data bit GPIO data bit GPIO data bit Core and I/O ground XRAM Differential Input strobe (bits 18-26) XRAM Data bit XRAM Data Valid Input This pin should come from the RLDRAM devices associated with XRAM_DATA[8:0]. XRAM Differential Output clock (bits 9-17) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Differential Output clock (bits 27-35) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Address bit XRAM Address bit XRAM Differential output command clock XRAM Address bit (MSB) Core and I/O ground Transmit Data bit (MSB) Transmit Data bit
AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30
XRAM2_DK1_P XRAM2_DATA_15 XRAM2_DATA_19 XRAM2_DATA_23 XRAM2_DK3_N XRAM2_DATA_29 XRAM2_DATA_31 XRAM2_DATA_30 XRAM2_ADDR_1 XRAM2_ADDR_7 XRAM2_CLK_N XRAM2_ADDR_20 VSS TX2_DATA_15_P TX2_DATA_15_N
O I/O I/O I/O O I/O I/O I/O O O O O GND O O
HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL 0V LVDS/HSTL LVDS/HSTL
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ01 AJ02 AJ03
Signal
GPIO2_1 GPIO2_4 GPIO2_VDD_PST GPIO2_10 GPIO2_VDD_PST GPIO2_25 GPIO2_VDD_PST GPIO2_31 GPIO2_VDD_PST GPIO2_40 GPIO2_VDD_PST XRAM2_DQS1_N XRAM2_VDD_PST XRAM2_DATA_3 XRAM2_VDD_PST XRAM2_DK1_N XRAM2_VDD_PST XRAM2_DATA_18 XRAM2_VDD_PST XRAM2_DK3_P XRAM2_VDD_PST XRAM2_DATA_33 XRAM2_VDD_PST XRAM2_ADDR_2 XRAM2_VDD_PST XRAM2_CLK_P XRAM2_VDD_PST XRAM2_ADDR_13 XRAM2_VDD_PST XRAM2_ADDR_16 GPIO2_2 GPIO2_5 GPIO2_7
Type
I/O I/O PWR I/O PWR I/O PWR I/O PWR I/O PWR I PWR I/O PWR O PWR I/O PWR O PWR I/O PWR O PWR O PWR O PWR O I/O I/O I/O
Signal Type
LVCMOS LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V LVCMOS 2.5V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL 1.8V HSTL LVCMOS LVCMOS LVCMOS
Description
GPIO data bit GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) GPIO data bit Connect to GPIO power (2.5V) XRAM Differential Input strobe (bits 9-17) Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Differential Output clock (bits 9-17) Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Differential Output clock (bits 27-35) Connect to XRAM I/O Power (1.8V) XRAM Data bit Connect to XRAM I/O Power (1.8V) XRAM Address bit Connect to XRAM I/O Power (1.8V) XRAM Command clock Connect to XRAM I/O Power (1.8V) XRAM Address bit Connect to XRAM I/O Power (1.8V) XRAM Address bit GPIO data bit GPIO data bit GPIO data bit
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Appendix A: External www..com Pins
Table 11-1 External Pins (Continued)
Pin Number
AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK01 AK02 AK03 AK04 AK05 AK06
Signal
VSS GPIO2_26 VSS GPIO2_32 VSS GPIO2_42 VSS GPIO2_47 XRAM2_DQS1_P XRAM2_DQS3_P XRAM2_DATA_2 XRAM2_DATA_8 VSS XRAM2_DATA_10 VSS XRAM2_DATA_24 VSS XRAM2_DATA_26 VSS XRAM2_CNTL_1 VSS XRAM2_BANK_1 VSS XRAM2_ADDR_8 VSS XRAM2_ADDR_14 XRAM2_ADDR_17 None GPIO2_6 GPIO2_13 GPIO2_24 GPIO2_27 GPIO2_30
Type
GND I/O GND I/O GND I/O GND I/O I I I/O I/O GND I/O GND I/O GND I/O GND O GND O GND O GND O O N/A I/O I/O I/O I/O I/O
Signal Type
0V LVCMOS 0V LVCMOS 0V LVCMOS 0V LVCMOS HSTL HSTL HSTL HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL 0V HSTL HSTL N/A LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
Description
Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit Core and I/O ground GPIO data bit XRAM Differential Input strobe (bits 9-17) XRAM Differential Input strobe (bits 27-35) XRAM Data bit XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Data bit Core and I/O ground XRAM Control bit Core and I/O ground XRAM Bank bit Core and I/O ground XRAM Address bit Core and I/O ground XRAM Address bit XRAM Address bit No ball GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit
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Arrix Family Data Sheet
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Appendix A: External Pins
Table 11-1 External Pins (Continued)
Pin Number
AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30
Signal
GPIO2_33 GPIO2_34 GPIO2_41 GPIO2_43 GPIO2_44 VSS XRAM2_DQS3_N XRAM2_DATA_5 XRAM2_DATA_4 XRAM2_DK0_N XRAM2_DK0_P XRAM2_DATA_12 XRAM2_DATA_11 XRAM2_DATA_25 XRAM2_DATA_27 XRAM2_DATA_32 XRAM2_CNTL_2 XRAM2_CNTL_0 XRAM2_BANK_2 XRAM2_BANK_0 XRAM2_ADDR_9 XRAM2_ADDR_15 XRAM2_ADDR_18 None
Type
I/O I/O I/O I/O I/O GND I I/O I/O O O I/O I/O I/O I/O I/O O O O O O O O N/A
Signal Type
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 0V HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL N/A
Description
GPIO data bit GPIO data bit GPIO data bit GPIO data bit GPIO data bit Core and I/O ground XRAM Differential Input strobe (bits 27-35) XRAM Data bit XRAM Data bit XRAM Differential Output clock (bits 0-8) XRAM Differential Output clock (bits 0-8) XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Data bit XRAM Control bit XRAM Control bit XRAM Bank bit XRAM Bank bit XRAM Address bit XRAM Address bit XRAM Address bit No ball
a. 16 mA drive for the GPIO clock
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Appendix A: External www..com Pins
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix B: Recommended Heat Sinks
Appendix B: Recommended Heat Sinks
CAUTION: Always check with the specific heat sink supplier for the latest information on their products. This section may not have the latest information. All names & trademarks are the property of their respective owners.
Table 12-1 Forced Convection Heat Sink Options TJ C TA C Power watts qJA C/watt qJC C/watt qCS C/watt Max qSA C/watt Heat Sink Example
250 LFM 85 85 85 85 115 115 115 115 85 85 85 85 115 115 115 115 40 40 40 40 40 40 40 40 55 55 55 55 55 55 55 55 10 20 25 30 10 20 25 30 10 20 25 30 10 20 25 30 4.5 2.25 1.8 1.5 7.5 3.75 3 2.5 3 1.5 1.2 1 6 3 2.4 2 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.95 1.7 1.25 0.95 6.95 3.2 2.45 1.95 2.45 0.95 0.65 0.45 5.45 2.45 1.85 1.45 500 LFM 85 85 85 85 115 115 40 40 40 40 40 40 10 20 25 30 10 20 4.5 2.25 1.8 1.5 7.5 3.75 0.45 0.45 0.45 0.45 0.45 0.45 0.1 0.1 0.1 0.1 0.1 0.1 3.95 1.7 1.25 0.95 6.95 3.2 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo P817151B00002 Tyco 1-1542007-3 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
Appendix B: Recommended Heat Sinks www..com
Table 12-1 Forced Convection Heat Sink Options (Continued) TJ C 115 115 85 85 85 85 115 115 115 115 TA C 40 40 55 55 55 55 55 55 55 55 Power watts 25 30 10 20 25 30 10 20 25 30 qJA C/watt 3 2.5 3 1.5 1.2 1 6 3 2.4 2 qJC C/watt 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 qCS C/watt 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Max qSA C/watt 2.45 1.95 2.45 0.95 0.65 0.45 5.45 2.45 1.85 1.45 750 LFM 85 85 85 85 115 115 115 115 85 85 85 85 115 115 115 115 40 40 40 40 40 40 40 40 55 55 55 55 55 55 55 55 10 20 25 30 10 20 25 30 10 20 25 30 10 20 25 30 4.5 2.25 1.8 1.5 7.5 3.75 3 2.5 3 1.5 1.2 1 6 3 2.4 2 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.95 1.7 1.25 0.95 6.95 3.2 2.45 1.95 2.45 0.95 0.65 0.45 5.45 2.45 1.85 1.45 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1127 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo P817151B00002 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 Heat Sink Example
1000 LFM 85 122 40 10 4.5 0.45 0.1 3.95 ThermaFlo B35351500000 www.mathstar.com
Arrix Family Field Programmable Object Array (FPOA)
Arrix Family Data Sheet
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Appendix B: Recommended Heat Sinks
Table 12-1 Forced Convection Heat Sink Options (Continued) TJ C 85 85 85 115 115 115 115 85 85 85 85 115 115 115 115 TA C 40 40 40 40 40 40 40 55 55 55 55 55 55 55 55 Power watts 20 25 30 10 20 25 30 10 20 25 30 10 20 25 30 qJA C/watt 2.25 1.8 1.5 7.5 3.75 3 2.5 3 1.5 1.2 1 6 3 2.4 2 qJC C/watt 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 qCS C/watt 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Max qSA C/watt 1.7 1.25 0.95 6.95 3.2 2.45 1.95 2.45 0.95 0.65 0.45 5.45 2.45 1.85 1.45 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo B35351500000 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 ThermaFlo EH1126 Heat Sink Example
Table 12-2 Natural Convection Heat Sink Options TJ C TA C Power watts qJA C/watt qJC C/watt qCS C/watt Max qSA C/watt Heat Sink Example
85 85 85 85 115 115 115 115
40 40 40 40 40 40 40 40
10 20 25 30 10 20 25 30
4.5 2.25 1.8 1.5 7.5 3.75 3 2.5
0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
3.95 1.7 1.25 0.95 6.95 3.2 2.45 1.95
ThermaFlo E3180 ThermaFlo E3180 ThermaFlo E3180 Active or Custom Passive ThermaFlo E3180 ThermaFlo E3180 ThermaFlo E3180 ThermaFlo E3180
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Arrix Family Field Programmable Object Array (FPOA)
123
Arrix Family Data Sheet
Appendix B: Recommended Heat Sinks www..com
Table 12-2 Natural Convection Heat Sink Options (Continued) TJ C TA C Power watts qJA C/watt qJC C/watt qCS C/watt Max qSA C/watt Heat Sink Example
85 85 85 85 115 115 115 115
55 55 55 55 55 55 55 55
10 20 25 30 10 20 25 30
3 1.5 1.2 1 6 3 2.4 2
0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
2.45 0.95 0.65 0.45 5.45 2.45 1.85 1.45
ThermaFlo E3180 Active or Custom Passive Active or Custom Passive Active or Custom Passive ThermaFlo E3180 ThermaFlo E3180 ThermaFlo E3180 ThermaFlo E3180
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Arrix Family Field Programmable Object Array (FPOA)
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Arrix Family Data Sheet
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Appendix C: Periphery Object Naming Convention
Appendix C: Periphery Object Naming Convention
The hardware and the software have different naming conventions when describing the periphery. The Data Sheet describes the periphery pinouts in terms of numeric values (e.g. XRAM1, XRAM2) whereas the COAST software describes the periphery objects in terms of their position on the grid (e.g. xram_9_n, xram_9_s). In order to reconcile these differences, the following table can be used:
Table 13-1 Periphery Object Naming Convention # Location in Periphery Pinout Notation XRAM 1 2 North side South side XRAM1_* XRAM2_* GPIO 1 2 North side South side GPIO1_* GPIO2_* RX 1 2 East side West side RX1_* RX2_* TX 1 2 East side West side TX1_* TX2_* IRAM 1 2 3 4 5 6 7 8 9 10 North side, east-most North side North side North side North side North side, west-most South side, east-most South side South side South side N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A iram_18_n iram_16_n iram_13_n iram_7_n iram_4_n iram_1_n iram_18_s iram_16_s iram_13_s iram_7_s tx_e_13 tx_w_5 rx_e_5 rx_w_13 gpio_11_n gpio_11_s xram_9_n xram_9_s COAST Notation
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Arrix Family Field Programmable Object Array (FPOA)
125
Arrix Family Data Sheet
Appendix C: Periphery Object Naming Convention www..com
Table 13-1 Periphery Object Naming Convention (Continued) # 11 12 Location in Periphery South side South side, west-most N/A N/A Control Object 1 West side N/A fpoa_control_w_19 Pinout Notation COAST Notation iram_4_s iram_1_s
126
Arrix Family Field Programmable Object Array (FPOA)
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